From: lkcl Date: Wed, 29 Mar 2023 22:00:00 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls012_v1~222 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed76ad094f0eeee2eefdf71848fd71ffa1c484ef;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index 7c72f5571..890f2c695 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -225,7 +225,7 @@ acts as if SV had not been applied at all to the instruction (an The fact that `VL` is dynamic and can be set to any value at runtime based on program conditions and behaviour means very specifically that `scalar identity behaviour` is **not** a redundant encoding. If the -only means by which VL cold be set was by way of static-compiled +only means by which VL could be set was by way of static-compiled immediates then this assertion would be false. VL should not be confused with MAXVL when understanding this key aspect of SimpleV. @@ -259,6 +259,11 @@ future versions of SV may involve 256 or greater registers. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Further discussion is out of scope for this version of SVP64. +Additionally, a future variant of SVP64 will be applied to the Scalar +(Quad-precision and 128-bit) VSX instructions. Element-width overrides +are an opportunity to expand the Power ISA to 256-bit, 512-bit and +1024-bit operations. + -------- \newpage{}