From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 00:36:38 +0000 (-0700)
Subject: Add comment
X-Git-Tag: working-ls180~1085^2~73
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed7be3e6b68521b2f147034f811a19bd7af86d1a;p=yosys.git

Add comment
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diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index ce77a3308..71112e3bc 100644
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -218,6 +218,10 @@ struct XilinxSrlPass : public Pass {
 				do {
 					auto pm = xilinx_srl_pm(module, module->selected_cells());
 					pm.ud_variable.minlen = minlen;
+					// Since `nusers` does not count module ports as a user,
+					//   and since `sigmap` does not always make such ports
+					//   the canonical signal.. need to maintain a pool these
+					//   ourselves
 					for (auto p : module->ports) {
 						auto w = module->wire(p);
 						if (w->port_output)