From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 30 Mar 2023 07:02:56 +0000 (-0700)
Subject: add addex to simulator
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed837783f433489920d97aaefac4f969eea9f8d6;p=openpower-isa.git

add addex to simulator

works, except it has incorrect CA/OV outputs, which I'll fix as part of fixing all add-like ops
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 5552d150..38b239dc 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1333,6 +1333,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         self.namespace['XER'] = self.spr['XER']
         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
         self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
+        self.namespace['OV'] = self.spr['XER'][XER_bits['OV']].value
+        self.namespace['OV32'] = self.spr['XER'][XER_bits['OV32']].value
         self.namespace['XLEN'] = xlen
 
         # add some SVSTATE convenience variables
diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 506b2dc7..90a91e1d 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -689,6 +689,7 @@ _insns = [
     "NONE", "add", "addc", "addco", "adde", "addeo",
     "addi", "addic", "addic.", "addis",
     "addme", "addmeo", "addo", "addze", "addzeo",
+    "addex",
     "addg6s",
     "and", "andc", "andi.", "andis.",
     "attn",
diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index 17bad9ba..8580e3f8 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -87,6 +87,35 @@ def check_addmeo_subfmeo_matches_reference(instr, case_filter, out):
 
 
 class ALUTestCase(TestAccumulatorBase):
+    def case_addex(self):
+        lst = [f"addex 3, 4, 5, 0"]
+        program = Program(lst, bigendian)
+        values = (*range(-2, 4), ~1 << 63, (1 << 63) - 1)
+        for ra in values:
+            ra %= 1 << 64
+            for rb in values:
+                rb %= 1 << 64
+                for ov in (0, 1):
+                    with self.subTest(ra=hex(ra), rb=hex(rb), ov=ov):
+                        initial_regs = [0] * 32
+                        initial_regs[4] = ra
+                        initial_regs[5] = rb
+                        initial_sprs = {}
+                        xer = SelectableInt(0, 64)
+                        xer[XER_bits['OV']] = ov
+                        initial_sprs[special_sprs['XER']] = xer
+                        e = ExpectedState(pc=4)
+                        v = ra + rb + ov
+                        v32 = (ra % (1 << 32)) + (rb % (1 << 32)) + ov
+                        ov = v >> 64
+                        ov32 = v32 >> 32
+                        e.intregs[3] = v % (1 << 64)
+                        e.intregs[4] = ra
+                        e.intregs[5] = rb
+                        e.ov = (ov32 << 1) | ov
+                        self.add_case(program, initial_regs,
+                                      initial_sprs=initial_sprs, expected=e)
+
     def case_nego_(self):
         lst = [f"nego. 3, 4"]
         initial_regs = [0] * 32