From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 31 Jan 2014 10:21:29 +0000 (+0100)
Subject: More changes to techlibs/common/simlib.v for LEC
X-Git-Tag: yosys-0.2.0~129
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed8ad99960992a2895e0965be1b84a1fdd5e4b8b;p=yosys.git

More changes to techlibs/common/simlib.v for LEC
---

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 07bf43d0b..c0c564fc7 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1124,14 +1124,19 @@ task tr_fetch;
 endtask
 
 always @(posedge pos_clk, posedge pos_arst) begin
-	if (pos_arst)
+	if (pos_arst) begin
 		state_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];
-	else
+		for (i = 0; i < STATE_BITS; i = i+1)
+			if (state_tmp[i] === 1'bz)
+				state_tmp[i] = 0;
+		state <= state_tmp;
+	end else begin
 		state_tmp = next_state;
-	for (i = 0; i < STATE_BITS; i = i+1)
-		if (state_tmp[i] === 1'bz)
-			state_tmp[i] = 0;
-	state <= state_tmp;
+		for (i = 0; i < STATE_BITS; i = i+1)
+			if (state_tmp[i] === 1'bz)
+				state_tmp[i] = 0;
+		state <= state_tmp;
+	end
 end
 
 always @(state, CTRL_IN) begin