From: lkcl <lkcl@web>
Date: Sun, 2 Oct 2022 13:35:10 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~250
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed8ec947bcb5449c8e4c34087f285253a3fd824b;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index ef40f2a58..522ee6f5a 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -128,7 +128,9 @@ that is near-identical to `divdeu` except that:
   the modulo in an implicit RS (similar to `maddedu`)
 
 RB, the divisor, remains 64 bit.  The instruction is therefore a 128/64
-division, producing a (pair) of 64 bit result(s).  Overflow conditions
+division, producing a (pair) of 64 bit result(s), in the same way that
+Intel [idiv](https://www.felixcloutier.com/x86/idiv) works.
+Overflow conditions
 are detected in exactly the same fashion as `divdeu`, except that rather
 than have `UNDEFINED` behaviour, RT is set to all ones and RS set to all
 zeros on overflow.
@@ -136,7 +138,8 @@ zeros on overflow.
 *Programmer's note: there are no Rc variants of any of these VA-Form
 instructions. `cmpi` will need to be used to detect overflow conditions:
 the saving in instruction count is that both RT and RS will have already
-been set to useful values needed as part of implementing Knuth's
+been set to useful values (all 1s and all zeros redpectively)
+needed as part of implementing Knuth's
 Algorithm D*
 
 For SVP64, given that this instruction is also 3-in 2-out 64-bit registers,