From: Dwarakanath Rajagopal Date: Tue, 1 May 2007 19:34:19 +0000 (+0000) Subject: i386.c (override_options): Accept k8-sse3... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ed99bffc4e1f0f8208b95cffc17486d72dab90e6;p=gcc.git i386.c (override_options): Accept k8-sse3... 2007-05-01 Dwarakanath Rajagopal * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3 and athlon64-sse3 as improved versions of k8, opteron and athlon64 with SSE3 instruction set support. * doc/invoke.texi: Likewise. From-SVN: r124339 --- diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 70a41dd5a12..6bd0c2dbf92 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1726,12 +1726,21 @@ override_options (void) {"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF}, + {"k8-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT + | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 + | PTA_SSE3 | PTA_NO_SAHF}, {"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF}, + {"opteron-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW + | PTA_64BIT | PTA_3DNOW_A | PTA_SSE + | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF}, {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF}, + {"athlon64-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW + | PTA_64BIT | PTA_3DNOW_A | PTA_SSE + | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF}, {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF}, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cc5feb9c8fb..9252a4666ae 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -9891,6 +9891,8 @@ instruction set support. @item k8, opteron, athlon64, athlon-fx AMD K8 core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.) +@item k8-sse3, opteron-sse3, athlon64-sse3 +Improved versions of k8, opteron and athlon64 with SSE3 instruction set support. @item amdfam10, barcelona AMD Family 10 core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSE4A, 3dNOW!, enhanced 3dNOW!, ABM and 64-bit