From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Wed, 9 Sep 2020 09:33:58 +0000 (+0100)
Subject: arch-arm: Fix ArmISA namespace requirement for TME instructions
X-Git-Tag: v20.1.0.0~48
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=edb1454fe0c584097ea5dbb25ec6b177e751e3f9;p=gem5.git

arch-arm: Fix ArmISA namespace requirement for TME instructions

This is needed after:

https://gem5-review.googlesource.com/c/public/gem5/+/34155

Change-Id: I8ef0b5ce9cd5ae5224331e1c9347fdd9e884a536
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34235
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 7aedd5558..a07788236 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -234,14 +234,14 @@ class MiscRegImplDefined64 : public MiscRegOp64
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
-class RegNone : public ArmStaticInst
+class RegNone : public ArmISA::ArmStaticInst
 {
   protected:
-    IntRegIndex dest;
+    ArmISA::IntRegIndex dest;
 
-    RegNone(const char *mnem, ExtMachInst _machInst,
-                     OpClass __opClass, IntRegIndex _dest) :
-        ArmStaticInst(mnem, _machInst, __opClass),
+    RegNone(const char *mnem, ArmISA::ExtMachInst _machInst,
+            OpClass __opClass, ArmISA::IntRegIndex _dest) :
+        ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
         dest(_dest)
     {}
 
diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index da228c4c2..30aff208e 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -40,6 +40,8 @@
 
  #include <sstream>
 
+using namespace ArmISA;
+
 namespace ArmISAInst {
 
 std::string
diff --git a/src/arch/arm/insts/tme64.hh b/src/arch/arm/insts/tme64.hh
index dada664e1..b75adc1e6 100644
--- a/src/arch/arm/insts/tme64.hh
+++ b/src/arch/arm/insts/tme64.hh
@@ -44,18 +44,19 @@
 
 namespace ArmISAInst {
 
-class MicroTmeOp : public MicroOp
+class MicroTmeOp : public ArmISA::MicroOp
 {
   protected:
-    MicroTmeOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) :
-               MicroOp(mnem, machInst, __opClass)
+    MicroTmeOp(const char *mnem, ArmISA::ExtMachInst machInst,
+               OpClass __opClass)
+      : ArmISA::MicroOp(mnem, machInst, __opClass)
     {}
 };
 
 class MicroTmeBasic64 : public MicroTmeOp
 {
   protected:
-    MicroTmeBasic64(const char *mnem, ExtMachInst machInst,
+    MicroTmeBasic64(const char *mnem, ArmISA::ExtMachInst machInst,
                     OpClass __opClass) :
                     MicroTmeOp(mnem, machInst, __opClass)
     {}
@@ -64,30 +65,30 @@ class MicroTmeBasic64 : public MicroTmeOp
                                     const Loader::SymbolTable *symtab) const;
 };
 
-class TmeImmOp64 : public ArmStaticInst
+class TmeImmOp64 : public ArmISA::ArmStaticInst
 {
   protected:
     uint64_t imm;
 
-    TmeImmOp64(const char *mnem, ExtMachInst machInst,
-               OpClass __opClass, uint64_t _imm) :
-                 ArmStaticInst(mnem, machInst, __opClass),
-                 imm(_imm)
+    TmeImmOp64(const char *mnem, ArmISA::ExtMachInst machInst,
+               OpClass __opClass, uint64_t _imm)
+      : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
+        imm(_imm)
     {}
 
     std::string generateDisassembly(Addr pc,
                                     const Loader::SymbolTable *symtab) const;
 };
 
-class TmeRegNone64 : public ArmStaticInst
+class TmeRegNone64 : public ArmISA::ArmStaticInst
 {
   protected:
-    IntRegIndex dest;
+    ArmISA::IntRegIndex dest;
 
-    TmeRegNone64(const char *mnem, ExtMachInst machInst,
-                 OpClass __opClass, IntRegIndex _dest) :
-                   ArmStaticInst(mnem, machInst, __opClass),
-                   dest(_dest)
+    TmeRegNone64(const char *mnem, ArmISA::ExtMachInst machInst,
+                 OpClass __opClass, ArmISA::IntRegIndex _dest)
+      : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
+        dest(_dest)
     {}
 
     std::string generateDisassembly(Addr pc,
@@ -97,7 +98,7 @@ class TmeRegNone64 : public ArmStaticInst
 class Tstart64 : public TmeRegNone64
 {
   public:
-    Tstart64(ExtMachInst, IntRegIndex);
+    Tstart64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);
 
     Fault execute(ExecContext *, Trace::InstRecord *) const;
     Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
@@ -107,7 +108,7 @@ class Tstart64 : public TmeRegNone64
 class Ttest64 : public TmeRegNone64
 {
   public:
-    Ttest64(ExtMachInst, IntRegIndex);
+    Ttest64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);
 
     Fault execute(ExecContext *, Trace::InstRecord *) const;
 };
@@ -115,7 +116,7 @@ class Ttest64 : public TmeRegNone64
 class Tcancel64 : public TmeImmOp64
 {
   public:
-    Tcancel64(ExtMachInst, uint64_t);
+    Tcancel64(ArmISA::ExtMachInst, uint64_t);
 
     Fault execute(ExecContext *, Trace::InstRecord *) const;
     Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
@@ -125,7 +126,7 @@ class Tcancel64 : public TmeImmOp64
 class MicroTfence64 : public MicroTmeBasic64
 {
   public:
-    MicroTfence64(ExtMachInst);
+    MicroTfence64(ArmISA::ExtMachInst);
 
     Fault execute(ExecContext *, Trace::InstRecord *) const;
     Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
@@ -135,7 +136,7 @@ class MicroTfence64 : public MicroTmeBasic64
 class MicroTcommit64 : public MicroTmeBasic64
 {
   public:
-    MicroTcommit64(ExtMachInst);
+    MicroTcommit64(ArmISA::ExtMachInst);
 
     Fault execute(ExecContext *, Trace::InstRecord *) const;
     Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
@@ -143,16 +144,17 @@ class MicroTcommit64 : public MicroTmeBasic64
 };
 
 
-class MacroTmeOp : public PredMacroOp
+class MacroTmeOp : public ArmISA::PredMacroOp
 {
   protected:
-    MacroTmeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass);
+    MacroTmeOp(const char *mnem, ArmISA::ExtMachInst _machInst,
+               OpClass __opClass);
 };
 
 class Tcommit64 : public MacroTmeOp
 {
   public:
-    Tcommit64(ExtMachInst _machInst);
+    Tcommit64(ArmISA::ExtMachInst _machInst);
 };
 
 } // namespace
diff --git a/src/arch/arm/insts/tme64classic.cc b/src/arch/arm/insts/tme64classic.cc
index 3ad6e0a52..b8fb627b3 100644
--- a/src/arch/arm/insts/tme64classic.cc
+++ b/src/arch/arm/insts/tme64classic.cc
@@ -38,6 +38,8 @@
 #include "arch/arm/faults.hh"
 #include "arch/arm/insts/tme64.hh"
 
+using namespace ArmISA;
+
 namespace ArmISAInst {
 
 Fault
diff --git a/src/arch/arm/insts/tme64ruby.cc b/src/arch/arm/insts/tme64ruby.cc
index a28c4e468..99481ba43 100644
--- a/src/arch/arm/insts/tme64ruby.cc
+++ b/src/arch/arm/insts/tme64ruby.cc
@@ -45,8 +45,9 @@
 #include "mem/packet_access.hh"
 #include "mem/request.hh"
 
-namespace ArmISAInst {
+using namespace ArmISA;
 
+namespace ArmISAInst {
 
 Fault
 Tstart64::initiateAcc(ExecContext *xc,