From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 Nov 2019 10:30:50 +0000 (+0100)
Subject: soc_core/soc_core_args: specify default cpu (vexriscv)
X-Git-Tag: 24jan2021_ls180~883
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=edb1731ef98a35262e838cfbf08b75a611843bf5;p=litex.git

soc_core/soc_core_args: specify default cpu (vexriscv)
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 346175f0..1a811ff7 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -540,7 +540,7 @@ class SoCCore(Module):
 def soc_core_args(parser):
     # CPU parameters
     parser.add_argument("--cpu-type", default=None,
-                        help="select CPU: {}".format(", ".join(iter(cpu.CPUS.keys()))))
+                        help="select CPU: {}, (default=vexriscv)".format(", ".join(iter(cpu.CPUS.keys()))))
     parser.add_argument("--cpu-variant", default=None,
                         help="select CPU variant, (default=standard)")
     parser.add_argument("--cpu-reset-address", default=None, type=int,