From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 1 Oct 2019 00:20:12 +0000 (-0700)
Subject: techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias
X-Git-Tag: working-ls180~1023^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=edc378072301dba7ee79dd1d64a825faf72a1d62;p=yosys.git

techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 08a1af2d5..8f8cff9fa 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -257,6 +257,12 @@ struct TechmapWorker
 					w->add_strpool_attribute(ID(src), extra_src_attrs);
 			}
 			design->select(module, w);
+
+			if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) {
+				IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
+				Wire *replace_w = module->addWire(replace_name, it.second);
+				module->connect(replace_w, w);
+			}
 		}
 
 		SigMap tpl_sigmap(tpl);
@@ -1198,6 +1204,10 @@ struct TechmapPass : public Pass {
 		log("\n");
 		log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
 		log("and attributes of the cell that is being replaced.\n");
+		log("A wire with a name of the form `_TECHMAP_REPLACE_.<suffix>` in the map file will\n");
+		log("cause a new wire alias to be created with its name set to the original but with\n");
+		log("its `_TECHMAP_REPLACE_' prefix to be substituted with the name of the cell being\n");
+		log("replaced.\n");
 		log("\n");
 		log("See 'help extract' for a pass that does the opposite thing.\n");
 		log("\n");