From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 14 Mar 2019 00:13:52 +0000 (-0700)
Subject: Move shregmap until after first techmap
X-Git-Tag: yosys-0.9~171^2~64
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=edca2f116373df7819ec68906ce74f15456168c2;p=yosys.git

Move shregmap until after first techmap
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 280c6b729..ce597ea4a 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -103,9 +103,9 @@ struct SynthXilinxPass : public Pass
 		log("        memory_map\n");
 		log("        dffsr2dff\n");
 		log("        dff2dffe\n");
-		log("        shregmap -init\n");
 		log("        opt -full\n");
 		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
+		log("        shregmap -init -params -enpol any_or_none\n");
 		log("        opt -fast\n");
 		log("\n");
 		log("    map_luts:\n");
@@ -223,9 +223,9 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "memory_map");
 			Pass::call(design, "dffsr2dff");
 			Pass::call(design, "dff2dffe");
-			Pass::call(design, "shregmap -init -params -enpol any_or_none");
 			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
+			Pass::call(design, "shregmap -init -params -enpol any_or_none");
 			Pass::call(design, "opt -fast");
 		}