From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 Mar 2013 00:09:00 +0000 (+0100)
Subject: adapt to migen changes
X-Git-Tag: 24jan2021_ls180~2575^2~111
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=edce543b14a8883245be304774857c4375d8ded9;p=litex.git

adapt to migen changes
---

diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py
index a4ad24d5..51163aa7 100644
--- a/examples/de0_nano/top.py
+++ b/examples/de0_nano/top.py
@@ -33,6 +33,7 @@
 #	I M P O R T 
 #==============================================================================
 from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
 from migen.fhdl import verilog, autofragment
 from migen.bus import csr
 from migen.bus.transactions import *
diff --git a/examples/de1/top.py b/examples/de1/top.py
index 45b45fc6..b0daa496 100644
--- a/examples/de1/top.py
+++ b/examples/de1/top.py
@@ -33,6 +33,7 @@
 #	I M P O R T 
 #==============================================================================
 from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
 from migen.fhdl import verilog, autofragment
 from migen.bus import csr
 from migen.bus.transactions import *
diff --git a/miscope/recorder.py b/miscope/recorder.py
index 16d5fa13..04283f2d 100644
--- a/miscope/recorder.py
+++ b/miscope/recorder.py
@@ -1,9 +1,10 @@
 from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
 from migen.bus import csr
 from migen.bank import description, csrgen
 from migen.bank.description import *
-from migen.corelogic.misc import optree
-from migen.corelogic.fsm import *
+from migen.genlib.misc import optree
+from migen.genlib.fsm import *
 
 class Storage:
 	# 
@@ -88,7 +89,7 @@ class Storage:
 		]
 		comb +=[self.done.eq((self._push_ptr == self._push_ptr_stop) & active_ongoing)]
 		
-		return Fragment(comb, sync, memories=[self._mem])
+		return Fragment(comb, sync, specials={self._mem})
 
 class Sequencer:
 	# 
diff --git a/miscope/tools/vcd.py b/miscope/tools/vcd.py
index c66811b3..3a44116a 100644
--- a/miscope/tools/vcd.py
+++ b/miscope/tools/vcd.py
@@ -1,8 +1,7 @@
 import sys
 import datetime
 
-sys.path.append("../../")
-from migScope.tools.conv import *
+from miscope.tools.conv import *
 
 def get_bits(values, width, low, high =None):
 	r = []
diff --git a/miscope/trigger.py b/miscope/trigger.py
index 9c0cda3b..55ace7c1 100644
--- a/miscope/trigger.py
+++ b/miscope/trigger.py
@@ -1,8 +1,9 @@
 from migen.fhdl.structure import *
+from migen.fhdl.specials import Memory
 from migen.bus import csr
 from migen.bank import description, csrgen
 from migen.bank.description import *
-from migen.corelogic.misc import optree
+from migen.genlib.misc import optree
 
 
 class RegParams:
@@ -233,7 +234,7 @@ class Sum:
 				self.o.eq(self._o)
 		]
 		comb += self.get_registers()
-		return Fragment(comb, memories=[self._mem])
+		return Fragment(comb, specials={self._mem})
 	
 	#
 	#Driver