From: Greta Yorsh Date: Fri, 19 Apr 2013 13:25:09 +0000 (+0100) Subject: arm.c (load_multiple_sequence, [...]): Fix spelling in two comments. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ede22fc330f055810555d867de5a8e3d3f94ad63;p=gcc.git arm.c (load_multiple_sequence, [...]): Fix spelling in two comments. 2013-04-19 Greta Yorsh * config/arm/arm.c (load_multiple_sequence, ldm_stm_operation_p): Fix spelling in two comments. From-SVN: r198093 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 439471d4d79..e395bd172d1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2013-04-19 Greta Yorsh + + * config/arm/arm.c (load_multiple_sequence, ldm_stm_operation_p): Fix + spelling in two comments. + 2013-04-19 Greta Yorsh PR target/56797 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7567afc719a..464d91c88ab 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -10491,7 +10491,7 @@ ldm_stm_operation_p (rtx op, bool load, enum machine_mode mode, /* Don't allow SP to be loaded unless it is also the base register. It guarantees that SP is reset correctly when an LDM instruction - is interruptted. Otherwise, we might end up with a corrupt stack. */ + is interrupted. Otherwise, we might end up with a corrupt stack. */ if (load && (REGNO (reg) == SP_REGNUM) && (REGNO (addr) != SP_REGNUM)) return false; @@ -10757,7 +10757,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, /* Don't allow SP to be loaded unless it is also the base register. It guarantees that SP is reset correctly when - an LDM instruction is interruptted. Otherwise, we might + an LDM instruction is interrupted. Otherwise, we might end up with a corrupt stack. */ if (unsorted_regs[i] == SP_REGNUM && base_reg != SP_REGNUM) return 0;