From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 9 Jun 2018 02:37:13 +0000 (+0100)
Subject: reorg
X-Git-Tag: convert-csv-opcode-to-binary~5246
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ede6497c0adc3942960d9b2dec8d40bbff4e6636;p=libreriscv.git

reorg
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index ec8a1318a..3a7317e34 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -107,7 +107,7 @@
    \item Amazingly, SIMD becomes (more) tolerable (no corner-cases)
    \item Modularity/Abstraction in both the h/w and the toolchain.
    \item "Reach" of registers accessible by Compressed is enhanced
-   \item Future: double the standard register file size(s).
+   \item Future: double the standard INT/FP register file sizes.
   \end{itemize}
   Note:
    \begin{itemize}
@@ -121,12 +121,13 @@
 \frame{\frametitle{How does Simple-V relate to RVV? What's different?}
 
  \begin{itemize}
-   \item RVV very heavy-duty (excellent for supercomputing)\vspace{10pt}
-   \item Simple-V abstracts parallelism (based on best of RVV)\vspace{10pt}
-   \item Graded levels: hardware, hybrid or traps (fit impl. need)\vspace{10pt}
-   \item Even Compressed become vectorised (RVV can't)\vspace{10pt}
+   \item RVV very heavy-duty (excellent for supercomputing)\vspace{8pt}
+   \item Simple-V abstracts parallelism (based on best of RVV)\vspace{8pt}
+   \item Graded levels: hardware, hybrid or traps (fit impl. need)\vspace{8pt}
+   \item Even Compressed become vectorised (RVV can't)\vspace{8pt}
+   \item No polymorphism in SV (too complex)\vspace{8pt}
   \end{itemize}
-  What Simple-V is not:\vspace{10pt}
+  What Simple-V is not:\vspace{4pt}
    \begin{itemize}
    \item A full supercomputer-level Vector Proposal
    \item A replacement for RVV (SV is designed to be over-ridden\\