From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Jul 2019 10:46:53 +0000 (+0100)
Subject: add comments on where DivPipeCoreSetupStage would be used
X-Git-Tag: ls180-24jan2020~927
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=edfea0f2c82642de8fecfa7b371372f9cbd9eaf4;p=ieee754fpu.git

add comments on where DivPipeCoreSetupStage would be used
---

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index f3f6667e..a08f5a5d 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -12,6 +12,7 @@ from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.getop import FPPipeContext
 
 
+# TODO: delete (replace by DivPipeCoreInputData)
 class FPDivStage0Data:
 
     def __init__(self, width, pspec):
diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py
index d62db0de..c9813e45 100644
--- a/src/ieee754/fpdiv/divstages.py
+++ b/src/ieee754/fpdiv/divstages.py
@@ -76,6 +76,13 @@ class FPDivStages(FPState, SimpleHandshake):
 
         if self.begin: # XXX check this
             divstages.append(FPDivStage0Mod(self.width, self.pspec))
+            # XXX if FPDivStage0Mod is to be used to convert from
+            # FPSCData into DivPipeCoreInputData, rather than
+            # DivPipeCoreSetupStage conforming *to* FPSCData format,
+            # then DivPipeCoreSetupStage needs to be added here:
+            # vvvvvvv
+            # FIXME divstages.append(DivPipeCoreSetupStage(something))
+            # ^^^^^^^
 
         for count in range(self.n_stages): # number of combinatorial stages
             divstages.append(FPDivStage1Mod(self.width, self.pspec))