From: Claire Wolf <clifford@clifford.at>
Date: Thu, 14 May 2020 16:06:18 +0000 (+0200)
Subject: Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
X-Git-Tag: working-ls180~557
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee0beb481db09e8faddf22109097649eac04486b;p=yosys.git

Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto

 ast: swap range regardless of range_left >= 0
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ee0beb481db09e8faddf22109097649eac04486b