From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 27 Mar 2018 12:12:57 +0000 (+0200)
Subject: Chenged "extensions_map" to "extensions_list" in hierarchy.cc
X-Git-Tag: yosys-0.8~141
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee3c12d6d9cbdb213c3c203d563c040867c70770;p=yosys.git

Chenged "extensions_map" to "extensions_list" in hierarchy.cc

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 21a232572..ba960faf4 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -173,14 +173,14 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 
 			for (auto &dir : libdirs)
 			{
-				static const std::map<std::string, std::string> extensions_map =
+				static const vector<pair<string, string>> extensions_list =
 				{
 					{".v", "verilog"},
 					{".sv", "verilog -sv"},
 					{".il", "ilang"}
 				};
 
-				for (auto &ext : extensions_map)
+				for (auto &ext : extensions_list)
 				{
 					filename = dir + "/" + RTLIL::unescape_id(cell->type) + ext.first;
 					if (check_file_exists(filename)) {