From: lkcl <lkcl@web>
Date: Thu, 24 Dec 2020 06:29:55 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~978
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee3e2ae4d757b411621eae9284040c04f09ae4a3;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index acc50ef64..e3c818f67 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -31,6 +31,19 @@ RISC-V RVV as of version 0.9 is over 180 instructions (more than the rest of RV6
 
 Even in OpenPOWER v3.0B, the Scalar Integer ISA is around 150 instructions, with IEEE754 FP adding approximately 80 more. VSX, being based on SIMD design principles, adds somewhere in the region of 600 more.
 
+The rest of this document builds on the above simple loop to add:
+
+* Vector-Scalar, Scalar-Vector and Scalar-Scalar operation
+* Traditional Vector operations (VSPLAT, VINSERT, VCOMPRESS etc)
+* Predication masks (essential for parallel if/else constructs)
+* 8, 16 and 32 bit integer operations, and both FP16 and BF16.
+* Fail-on-first (introduced in ARM SVE2)
+* A new concept known as "Twin Predication"
+
+All of this is *without modifying the OpenPOWER v3.0B ISA*, except to add "wrapping context", similar to how v3.1B 64 Prefixes work.
+
+
+