From: shuffle2 <godisgovernment@gmail.com>
Date: Mon, 4 May 2020 08:10:09 +0000 (-0700)
Subject: diamond: quiet warning about missing clkin freq for EHXPLLL
X-Git-Tag: 24jan2021_ls180~393^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee413527ac080a53837664fd54dc31987933d10e;p=litex.git

diamond: quiet warning about missing clkin freq for EHXPLLL

FREQUENCY_PIN_CLKI should be given in mhz
---

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 97f83c7b..321768e6 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -676,6 +676,7 @@ class ECP5PLL(Module):
         clkfb  = Signal()
         self.params.update(
             attr=[
+                ("FREQUENCY_PIN_CLKI",     str(self.clkin_freq/1e6)),
                 ("ICP_CURRENT",            "6"),
                 ("LPF_RESISTOR",          "16"),
                 ("MFG_ENABLE_FILTEROPAMP", "1"),