From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 6 Sep 2020 11:50:47 +0000 (+0100)
Subject: move DEC and TB from StateRegs to FastRegs for several reasons
X-Git-Tag: semi_working_ecp5~173
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee491651861ed89c44ced180189656b8a80fbee0;p=soc.git

move DEC and TB from StateRegs to FastRegs for several reasons
first: SPR pipeline already has fast1 read/write
second: a new DecodeStateIn/Out object would be needed
        instead just add FastRegs.DEC/TB to DecodeA/Out
third: there is probably a third somewhere
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 83238391..66cc8d97 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -149,7 +149,12 @@ class DecodeA(Elaboratable):
                     with m.Case(SPR.XER.value):
                         comb += self.fast_out.data.eq(FastRegs.XER)
                         comb += self.fast_out.ok.eq(1)
-                        pass  # do nothing
+                    with m.Case(SPR.DEC.value):
+                        comb += self.fast_out.data.eq(FastRegs.DEC)
+                        comb += self.fast_out.ok.eq(1)
+                    with m.Case(SPR.TB.value):
+                        comb += self.fast_out.data.eq(FastRegs.TB)
+                        comb += self.fast_out.ok.eq(1)
                     # : map to internal SPR numbers
                     # XXX TODO: dec and tb not to go through mapping.
                     with m.Default():
@@ -332,7 +337,12 @@ class DecodeOut(Elaboratable):
                         with m.Case(SPR.XER.value):
                             comb += self.fast_out.data.eq(FastRegs.XER)
                             comb += self.fast_out.ok.eq(1)
-                            pass  # do nothing
+                        with m.Case(SPR.TB.value):
+                            comb += self.fast_out.data.eq(FastRegs.TB)
+                            comb += self.fast_out.ok.eq(1)
+                        with m.Case(SPR.DEC.value):
+                            comb += self.fast_out.data.eq(FastRegs.DEC)
+                            comb += self.fast_out.ok.eq(1)
                         # : map to internal SPR numbers
                         # XXX TODO: dec and tb not to go through mapping.
                         with m.Default():
diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 65caf014..6c1e76e7 100644
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -91,7 +91,7 @@ def regspec_decode_read(e, regfile, name):
     if regfile == 'STATE':
         # STATE register numbering is *unary* encoded
         PC = 1<<StateRegs.PC
-        MSR = 1<<Stateegs.MSR
+        MSR = 1<<StateRegs.MSR
         if name in ['cia', 'nia']:
             return Const(1), PC # TODO: detect read-conditions
         if name == 'msr':
diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py
index b1262795..523bff25 100644
--- a/src/soc/fu/spr/main_stage.py
+++ b/src/soc/fu/spr/main_stage.py
@@ -36,7 +36,6 @@ class SPRMainStage(PipeModBase):
         so_i, ov_i, ca_i = self.i.xer_so, self.i.xer_ov, self.i.xer_ca
         so_o, ov_o, ca_o = self.o.xer_so, self.o.xer_ov, self.o.xer_ca
         o, spr1_o, fast1_o = self.o.o, self.o.spr1, self.o.fast1
-        state_i, state_o = self.i.state, self.o.state
 
         # take copy of D-Form TO field
         x_fields = self.fields.FormXFX
@@ -50,7 +49,7 @@ class SPRMainStage(PipeModBase):
                 with m.Switch(spr):
                     # fast SPRs first
                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0,
-                                SPR.SRR1, SPR.XER):
+                                SPR.SRR1, SPR.XER, SPR.DEC):
                         comb += fast1_o.data.eq(a_i)
                         comb += fast1_o.ok.eq(1)
                         # XER is constructed
@@ -66,10 +65,6 @@ class SPRMainStage(PipeModBase):
                             comb += ca_o.data[0].eq(a_i[63-XER_bits['CA']])
                             comb += ca_o.data[1].eq(a_i[63-XER_bits['CA32']])
                             comb += ca_o.ok.eq(1)
-                    # STATE SPRs (dec, tb)
-                    with m.Case(SPR.DEC):
-                        comb += state_o.data.eq(a_i)
-                        comb += state_o.ok.eq(1)
 
                     # slow SPRs TODO
 
@@ -79,7 +74,7 @@ class SPRMainStage(PipeModBase):
                 with m.Switch(spr):
                     # fast SPRs first
                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1,
-                                SPR.XER):
+                                SPR.XER, SPR.DEC, SPR.TB):
                         comb += o.data.eq(fast1_i)
                         with m.If(spr == SPR.XER):
                             # bits 0:31 and 35:43 are treated as reserved
@@ -94,11 +89,8 @@ class SPRMainStage(PipeModBase):
                             # carry
                             comb += o[63-XER_bits['CA']].eq(ca_i[0])
                             comb += o[63-XER_bits['CA32']].eq(ca_i[1])
-                    # STATE SPRs (dec, tb)
-                    with m.Case(SPR.DEC, SPR.TB):
-                        comb += o.data.eq(state_i)
                     with m.Case(SPR.TBU):
-                        comb += o.data[0:32].eq(state_i[32:64])
+                        comb += o.data[0:32].eq(fast1_i[32:64])
 
                     # slow SPRs TODO
 
diff --git a/src/soc/fu/spr/pipe_data.py b/src/soc/fu/spr/pipe_data.py
index bdd0608d..b66c35a0 100644
--- a/src/soc/fu/spr/pipe_data.py
+++ b/src/soc/fu/spr/pipe_data.py
@@ -19,7 +19,6 @@ class SPRInputData(IntegerData):
     regspec = [('INT', 'ra', '0:63'),        # RA
                ('SPR', 'spr1', '0:63'),      # SPR (slow)
                ('FAST', 'fast1', '0:63'),    # SPR (fast: LR, CTR etc)
-               ('STATE', 'state', '0:63'),   # SPR (state: DEC, TB)
                ('XER', 'xer_so', '32'),      # XER bit 32: SO
                ('XER', 'xer_ov', '33,44'),   # XER bit 34/45: CA/CA32
                ('XER', 'xer_ca', '34,45')]   # bit0: ov, bit1: ov32
@@ -33,7 +32,6 @@ class SPROutputData(IntegerData):
     regspec = [('INT', 'o', '0:63'),        # RT
                ('SPR', 'spr1', '0:63'),     # SPR (slow)
                ('FAST', 'fast1', '0:63'),   # SPR (fast: LR, CTR etc)
-               ('STATE', 'state', '0:63'),   # SPR (state: DEC, TB)
                ('XER', 'xer_so', '32'),     # XER bit 32: SO
                ('XER', 'xer_ov', '33,44'),  # XER bit 34/45: CA/CA32
                ('XER', 'xer_ca', '34,45')]  # bit0: ov, bit1: ov32
diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 9ffde7b3..23515dd9 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -35,7 +35,7 @@ class StateRegs(RegFileArray):
     State regfile  - PC, MSR, DEC, TB and later SimpleV VL
 
     * QTY 4of 64-bit registers
-    * 5R4W
+    * 3R2W
     * Array-based unary-indexed (not binary-indexed)
     * write-through capability (read on same cycle as write)
 
@@ -43,24 +43,16 @@ class StateRegs(RegFileArray):
     will probably have to also add one so it can get at the MSR as well.
     (d_rd2)
 
-    Note: r/w state are used by SPR for MTSPR / MFSPR.
-    Note: r/w issue are used by issuer to increment/decrement TB/DEC.
     """
     PC = 0
     MSR = 1
-    DEC = 2
-    TB = 3
     def __init__(self):
         super().__init__(64, 4)
         self.w_ports = {'nia': self.write_port("nia"),
                         'msr': self.write_port("msr"),
-                        'state': self.read_port("state"), # writing DEC/TB
-                        'issue': self.read_port("issue"), # writing DEC/TB
                         'd_wr1': self.write_port("d_wr1")} # writing PC (issuer)
         self.r_ports = {'cia': self.read_port("cia"), # reading PC (issuer)
                         'msr': self.read_port("msr"), # reading MSR (issuer)
-                        'state': self.read_port("state"), # reading DEC/TB
-                        'issue': self.read_port("issue"), # reading DEC/TB
                         }
 
 
@@ -88,12 +80,14 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
 class FastRegs(RegFileMem): #RegFileArray):
     """FastRegs
 
-    FAST regfile  - CTR, LR, TAR, SRR1, SRR2, XER
+    FAST regfile  - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC
 
     * QTY 6of 64-bit registers
-    * 2R1W
+    * 3R2W
     * Array-based unary-indexed (not binary-indexed)
     * write-through capability (read on same cycle as write)
+
+    Note: r/w issue are used by issuer to increment/decrement TB/DEC.
     """
     CTR = 0
     LR = 1
@@ -101,12 +95,16 @@ class FastRegs(RegFileMem): #RegFileArray):
     SRR0 = 3
     SRR1 = 4
     XER = 5 # non-XER bits
+    DEC = 6
+    TB = 7
     def __init__(self):
-        super().__init__(64, 6)
+        super().__init__(64, 8)
         self.w_ports = {'fast1': self.write_port("dest1"),
+                        'issue': self.write_port("issue"), # writing DEC/TB
                        }
         self.r_ports = {'fast1': self.read_port("src1"),
                         'fast2': self.read_port("src2"),
+                        'issue': self.read_port("issue"), # reading DEC/TB
                         }