From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 28 Jul 2014 08:10:08 +0000 (+0200)
Subject: Fixed signdness detection of expressions with bit- and part-selects
X-Git-Tag: yosys-0.4~382
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee65dea738fefbf44b91a2ac10f9a93b35115af6;p=yosys.git

Fixed signdness detection of expressions with bit- and part-selects
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 064aec93f..95e15903b 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -599,6 +599,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 				delete right_at_zero_ast;
 			} else
 				this_width = range->range_left - range->range_right + 1;
+			sign_hint = false;
 		} else
 			width_hint = std::max(width_hint, this_width);
 		if (!id_ast->is_signed)