From: Segher Boessenkool Date: Mon, 11 Jun 2018 15:48:48 +0000 (+0200) Subject: rs6000: Put constraints on the correct operand in movdi (PR85755) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee6760c2917461ff7dd0f49d80a594fecd476f38;p=gcc.git rs6000: Put constraints on the correct operand in movdi (PR85755) Some of the mov* patterns use ^ and $ constraint modifiers, which mean give a penalty to this alternative if this operand needs a reload. They are meant here to give a penalty if a register operand needs reloading (because it needs to be in a different kind of register), not when a memory operand needs reloading (which is easy and cheap to do). This patch fixes the movdi patterns. This fixes PR85755. The following are changed (name, old constraints, new constraints): FPR store ^m := d m := ^d FPR move ^d := d ^d := ^d AVX store ^wY := wb wY := ^wb AVX store $Z := wv Z := $wv VSX move ^wi := wi ^wi := ^wi PR target/85755 * config/rs6000/rs6000.md (*movdi_internal32): Put constraint modifiers on the correct operand. (*movdi_internal64): Ditto. --- gcc/config/rs6000/rs6000.md | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index a2605a0..f06591f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8567,16 +8567,16 @@ (define_insn_and_split "reload_gpr_from_vsxsf" (define_insn "*movdi_internal32" [(set (match_operand:DI 0 "nonimmediate_operand" - "=Y, r, r, ^m, ^d, ^d, - r, ^wY, $Z, ^wb, $wv, ^wi, + "=Y, r, r, m, ^d, ^d, + r, wY, Z, ^wb, $wv, ^wi, *wo, *wo, *wv, *wi, *wi, *wv, *wv") (match_operand:DI 1 "input_operand" - "r, Y, r, d, m, d, - IJKnGHF, wb, wv, wY, Z, wi, - Oj, wM, OjwM, Oj, wM, wS, - wB"))] + "r, Y, r, ^d, m, ^d, + IJKnGHF, ^wb, $wv, wY, Z, ^wi, + Oj, wM, OjwM, Oj, wM, wS, + wB"))] "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) @@ -8643,17 +8643,17 @@ (define_split (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" "=YZ, r, r, r, r, r, - ^m, ^d, ^d, ^wY, $Z, $wb, + m, ^d, ^d, wY, Z, $wb, $wv, ^wi, *wo, *wo, *wv, *wi, *wi, *wv, *wv, r, *h, *h, ?*r, ?*wg, ?*r, ?*wj") (match_operand:DI 1 "input_operand" - "r, YZ, r, I, L, nF, - d, m, d, wb, wv, wY, - Z, wi, Oj, wM, OjwM, Oj, - wM, wS, wB, *h, r, 0, - wg, r, wj, r"))] + "r, YZ, r, I, L, nF, + ^d, m, ^d, ^wb, $wv, wY, + Z, ^wi, Oj, wM, OjwM, Oj, + wM, wS, wB, *h, r, 0, + wg, r, wj, r"))] "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) -- 1.8.3.1 From-SVN: r261435 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4032e6c079c..51b3e913d32 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2018-06-11 Segher Boessenkool + + PR target/85755 + * config/rs6000/rs6000.md (*movdi_internal32): Put constraint modifiers + on the correct operand. + (*movdi_internal64): Ditto. + 2018-06-11 Martin Liska PR tree-optimization/86089 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index fc526d020a8..b0a88a91211 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8517,16 +8517,16 @@ (define_insn "*movdi_internal32" [(set (match_operand:DI 0 "nonimmediate_operand" - "=Y, r, r, ^m, ^d, ^d, - r, ^wY, $Z, ^wb, $wv, ^wi, + "=Y, r, r, m, ^d, ^d, + r, wY, Z, ^wb, $wv, ^wi, *wo, *wo, *wv, *wi, *wi, *wv, *wv") (match_operand:DI 1 "input_operand" - "r, Y, r, d, m, d, - IJKnGHF, wb, wv, wY, Z, wi, - Oj, wM, OjwM, Oj, wM, wS, - wB"))] + "r, Y, r, ^d, m, ^d, + IJKnGHF, ^wb, $wv, wY, Z, ^wi, + Oj, wM, OjwM, Oj, wM, wS, + wB"))] "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) @@ -8593,17 +8593,17 @@ (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" "=YZ, r, r, r, r, r, - ^m, ^d, ^d, ^wY, $Z, $wb, + m, ^d, ^d, wY, Z, $wb, $wv, ^wi, *wo, *wo, *wv, *wi, *wi, *wv, *wv, r, *h, *h, ?*r, ?*wg, ?*r, ?*wj") (match_operand:DI 1 "input_operand" - "r, YZ, r, I, L, nF, - d, m, d, wb, wv, wY, - Z, wi, Oj, wM, OjwM, Oj, - wM, wS, wB, *h, r, 0, - wg, r, wj, r"))] + "r, YZ, r, I, L, nF, + ^d, m, ^d, ^wb, $wv, wY, + Z, ^wi, Oj, wM, OjwM, Oj, + wM, wS, wB, *h, r, 0, + wg, r, wj, r"))] "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode)