From: lkcl <lkcl@web>
Date: Tue, 20 Oct 2020 13:49:23 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~2008
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee6f5a114e18f1dd1c8ee8f594d8f683d8340882;p=libreriscv.git

---

diff --git a/conferences.mdwn b/conferences.mdwn
index ac569be57..2017c8a1a 100644
--- a/conferences.mdwn
+++ b/conferences.mdwn
@@ -59,8 +59,7 @@
   - VSX is SIMD and is considered harmful
   - https://www.sigarch.org/simd-instructions-considered-harmful/
 * Developed in python HDL called "nmigen"
-  - OO programming techniques can be deployed
-  - Impossible to do in VHDL or Verilog
+  - OO programming techniques can be used (not possible in VHDL/Verilog)
   - yosys converts nmigen to verilog for standard tools.
 
 ## What is being developed? (Roadmap)