From: whitequark <whitequark@whitequark.org>
Date: Mon, 13 Apr 2020 17:04:13 +0000 (+0000)
Subject: back.rtlil: don't emit connections to zero width ports.
X-Git-Tag: working_23jun2020~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee73d39b8d6817f98b1aa9d29e68d0012e37bcc9;p=nmigen.git

back.rtlil: don't emit connections to zero width ports.

Fixes #335.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index f683687..90c5ed9 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -880,7 +880,8 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
                 if not isinstance(subfragment, ir.Instance):
                     for signal in value._rhs_signals():
                         compiler_state.resolve_curr(signal, prefix=sub_name)
-                sub_ports[port] = rhs_compiler(value)
+                if len(value) > 0:
+                    sub_ports[port] = rhs_compiler(value)
 
             module.cell(sub_type, name=sub_name, ports=sub_ports, params=sub_params,
                         attrs=subfragment.attrs)