From: Luke Kenneth Casson Leighton Date: Tue, 2 Jun 2020 22:39:43 +0000 (+0100) Subject: argh - bad hack, detecting when there are no registers to write, in MultiCompUnit X-Git-Tag: div_pipeline~637^2~26 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee7ab36616cb650a344a4c0eeeba69423cce55f7;p=soc.git argh - bad hack, detecting when there are no registers to write, in MultiCompUnit --- diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index baebed09..4c1f0191 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -204,6 +204,12 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): m.d.comb += wr_any.eq(self.wr.go.bool()) m.d.comb += req_done.eq(wr_any & ~self.alu.n.ready_i & \ ((req_l.q & self.wrmask) == 0)) + # argh, complicated hack: if there are no regs to write, + # instead of waiting for regs that are never going to happen, + # we indicate "done" when the ALU is "done" + with m.If((self.wrmask == 0) & \ + self.alu.n.ready_i & self.alu.n.valid_o & self.busy_o): + m.d.comb += req_done.eq(1) # shadow/go_die reset = Signal(reset_less=True) diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 2c4b43e0..eb419abd 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -169,6 +169,10 @@ class TestRunner(FHDLTestCase): wr_rel_o = yield cu.wr.rel print ("before inputs, rd_rel, wr_rel: ", bin(rd_rel_o), bin(wr_rel_o)) + assert wr_rel_o == 0, "wr.rel %s must be zero. "\ + "previous instr not written all regs\n"\ + "respec %s" % \ + (bin(wr_rel_o), cu.rwid[1]) yield from set_cu_inputs(cu, inp) yield rd_rel_o = yield cu.rd.rel @@ -182,6 +186,7 @@ class TestRunner(FHDLTestCase): yield from sim.call(opname) index = sim.pc.CIA.value//4 + yield Settle() # get all outputs (one by one, just "because") res = yield from get_cu_outputs(cu, code)