From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 02:08:33 +0000 (-0700)
Subject: IdString::str().substr() -> IdString::substr()
X-Git-Tag: working-ls180~1151^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee7c970367c68fe1a02a237ed01f2845a03cf9b2;p=yosys.git

IdString::str().substr() -> IdString::substr()
---

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index e947125bf..b27780fae 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2319,7 +2319,7 @@ skip_dynamic_range_lvalue_expansion:;
 				if (attr.first.str().rfind("\\via_celltype_defparam_", 0) == 0)
 				{
 					AstNode *cell_arg = new AstNode(AST_PARASET, attr.second->clone());
-					cell_arg->str = RTLIL::escape_id(attr.first.str().substr(strlen("\\via_celltype_defparam_")));
+					cell_arg->str = RTLIL::escape_id(attr.first.substr(strlen("\\via_celltype_defparam_")));
 					cell->children.push_back(cell_arg);
 				}
 
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index ff5c3b6a1..1319225ff 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -203,7 +203,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 			int idx = std::stoi(cell->type.substr(pos_idx + 1, pos_num));
 			int num = std::stoi(cell->type.substr(pos_num + 1, pos_type));
 			array_cells[cell] = std::pair<int, int>(idx, num);
-			cell->type = cell->type.str().substr(pos_type + 1);
+			cell->type = cell->type.substr(pos_type + 1);
 		}
 		dict<RTLIL::IdString, RTLIL::Module*> interfaces_to_add_to_submodule;
 		dict<RTLIL::IdString, RTLIL::IdString> modports_used_in_submodule;