From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 20 Mar 2017 07:48:16 +0000 (-0700)
Subject: PUM -> SUM; expose MXR to S-mode
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee80f2851aef29f8744b5a73afe45a1927c82b37;p=riscv-isa-sim.git

PUM -> SUM; expose MXR to S-mode
---

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 1b9883e..60ee674 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -17,7 +17,7 @@
 #define MSTATUS_FS          0x00006000
 #define MSTATUS_XS          0x00018000
 #define MSTATUS_MPRV        0x00020000
-#define MSTATUS_PUM         0x00040000
+#define MSTATUS_SUM         0x00040000
 #define MSTATUS_MXR         0x00080000
 #define MSTATUS_TVM         0x00100000
 #define MSTATUS_TW          0x00200000
@@ -32,7 +32,8 @@
 #define SSTATUS_SPP         0x00000100
 #define SSTATUS_FS          0x00006000
 #define SSTATUS_XS          0x00018000
-#define SSTATUS_PUM         0x00040000
+#define SSTATUS_SUM         0x00040000
+#define SSTATUS_MXR         0x00080000
 #define SSTATUS32_SD        0x80000000
 #define SSTATUS64_SD        0x8000000000000000
 
diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 06bc11b..0b28f2f 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -162,7 +162,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
     return addr & ((reg_t(2) << (proc->xlen-1))-1); // zero-extend from xlen
 
   bool supervisor = mode == PRV_S;
-  bool pum = get_field(proc->state.mstatus, MSTATUS_PUM);
+  bool sum = get_field(proc->state.mstatus, MSTATUS_SUM);
   bool mxr = get_field(proc->state.mstatus, MSTATUS_MXR);
 
   // verify bits xlen-1:va_bits-1 are all equal
@@ -188,7 +188,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
 
     if (PTE_TABLE(pte)) { // next level of page table
       base = ppn << PGSHIFT;
-    } else if ((pte & PTE_U) ? supervisor && pum : !supervisor) {
+    } else if ((pte & PTE_U) ? supervisor && !sum : !supervisor) {
       break;
     } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
       break;
diff --git a/riscv/processor.cc b/riscv/processor.cc
index f326f91..aa69bdc 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -293,11 +293,11 @@ void processor_t::set_csr(int which, reg_t val)
       break;
     case CSR_MSTATUS: {
       if ((val ^ state.mstatus) &
-          (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
+          (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
         mmu->flush_tlb();
 
       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
-                 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
+                 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
                  | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
                  | MSTATUS_TSR | (ext ? MSTATUS_XS : 0);
 
@@ -353,7 +353,7 @@ void processor_t::set_csr(int which, reg_t val)
       break;
     case CSR_SSTATUS: {
       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
-                 | SSTATUS_XS | SSTATUS_PUM;
+                 | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
     }
     case CSR_SIP: {
@@ -512,7 +512,7 @@ reg_t processor_t::get_csr(int which)
     case CSR_MCOUNTEREN: return state.mcounteren;
     case CSR_SSTATUS: {
       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
-                 | SSTATUS_XS | SSTATUS_PUM;
+                 | SSTATUS_XS | SSTATUS_SUM;
       reg_t sstatus = state.mstatus & mask;
       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
           (sstatus & SSTATUS_XS) == SSTATUS_XS)