From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Oct 2018 14:09:21 +0000 (+0100)
Subject: add comment explaining why invert isnt done in zeroing test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee8427fb74c004cef601ef847cf86ab1af3a9c61;p=riscv-isa-sim.git

add comment explaining why invert isnt done in zeroing test
(already inverted basically)
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 475c8e5..2feaf48 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -46,6 +46,7 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
       insn.reset_vloop_check();
       #include INCLUDEFILE
 #if defined(USING_REG_RD) || defined(USING_REG_FRD)
+      // don't check inversion here as dest_pred has already been inverted
       if (zeroing && ((dest_pred & (1<<voffs)) == 0))
       {
           // insn._rd() would be predicated: have to use insn._rd() here