From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 30 Jun 2015 15:11:46 +0000 (+0200)
Subject: Added logic-loop error handling to freduce
X-Git-Tag: yosys-0.6~237
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee9188a5b4013f22d2694d4c3e5bb7d08438bfb3;p=yosys.git

Added logic-loop error handling to freduce
---

diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 8a5301ec3..a60de4ee0 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -229,6 +229,7 @@ struct PerformReduction
 	SigMap &sigmap;
 	drivers_t &drivers;
 	std::set<std::pair<RTLIL::SigBit, RTLIL::SigBit>> &inv_pairs;
+	pool<SigBit> recursion_guard;
 
 	ezSatPtr ez;
 	SatGen satgen;
@@ -246,6 +247,15 @@ struct PerformReduction
 		if (sigdepth.count(out) != 0)
 			return sigdepth.at(out);
 
+		if (recursion_guard.count(out)) {
+			string loop_signals;
+			for (auto loop_bit : recursion_guard)
+				loop_signals += string(" ") + log_signal(loop_bit);
+			log_error("Found logic loop:%s\n", loop_signals.c_str());
+		}
+
+		recursion_guard.insert(out);
+
 		if (drivers.count(out) != 0) {
 			std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out);
 			if (celldone.count(drv.first) == 0) {
@@ -264,6 +274,7 @@ struct PerformReduction
 			sigdepth[out] = 0;
 		}
 
+		recursion_guard.erase(out);
 		return sigdepth.at(out);
 	}