From: Tim Newsome <tim@sifive.com>
Date: Wed, 4 May 2016 16:40:20 +0000 (-0700)
Subject: Fix off-by-two in general read registers.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee96c255f12477b1762426ceb7bbd83370c899cd;p=riscv-isa-sim.git

Fix off-by-two in general read registers.

Now the exit test passes!
---

diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc
index d7cf162..d3f2d4d 100644
--- a/riscv/gdbserver.cc
+++ b/riscv/gdbserver.cc
@@ -382,7 +382,7 @@ class general_registers_read_op_t : public operation_t
 
       gs.send(((uint64_t) gs.read_debug_ram(1) << 32) | gs.read_debug_ram(0));
 
-      unsigned int current_reg = 2 * step - 1;
+      unsigned int current_reg = 2 * step + 1;
       unsigned int i = 0;
       if (current_reg == S1) {
         gs.write_debug_ram(i++, ld(S1, 0, (uint16_t) DEBUG_RAM_END - 8));
diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 44ff97a..9b623ae 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -74,7 +74,6 @@ const uint16_t* mmu_t::fetch_slow_path(reg_t vaddr)
 void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
 {
   reg_t paddr = translate(addr, LOAD);
-  fprintf(stderr, "load_slow_path 0x%lx -> 0x%lx\n", addr, paddr);
   if (sim->addr_is_mem(paddr)) {
     memcpy(bytes, sim->addr_to_mem(paddr), len);
     if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
@@ -89,7 +88,6 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
 void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
 {
   reg_t paddr = translate(addr, STORE);
-  fprintf(stderr, "store_slow_path 0x%lx -> 0x%lx\n", addr, paddr);
   if (sim->addr_is_mem(paddr)) {
     memcpy(sim->addr_to_mem(paddr), bytes, len);
     if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
@@ -147,7 +145,6 @@ reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
 
     void* ppte = sim->addr_to_mem(pte_addr);
     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
-    fprintf(stderr, "walk pte entry 0x%lx = 0x%lx\n", pte_addr, pte);
     reg_t ppn = pte >> PTE_PPN_SHIFT;
 
     if (PTE_TABLE(pte)) { // next level of page table
@@ -162,7 +159,6 @@ reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
       reg_t vpn = addr >> PGSHIFT;
       reg_t value = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
-      fprintf(stderr, "walk 0x%lx -> 0x%lx\n", addr, value);
       return value;
     }
   }
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 4c4e3dd..d43defc 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -279,7 +279,6 @@ static bool validate_vm(int max_xlen, reg_t vm)
 
 void processor_t::set_csr(int which, reg_t val)
 {
-  fprintf(stderr, "set_csr(0x%x, 0x%lx)\n", which, val);
   val = zext_xlen(val);
   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;