From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 24 Aug 2019 01:14:06 +0000 (-0700)
Subject: Also add first.Q to chain_bits since variable length
X-Git-Tag: working-ls180~1085^2~25
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ee9f6e6243cbea9efbd0f1b0a236e33ac6a0450e;p=yosys.git

Also add first.Q to chain_bits since variable length
---

diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index d41bd3be9..76134de1a 100644
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -196,6 +196,7 @@ code clk_port en_port
 		en_port = \EN;
 	else log_abort();
 
+	chain_bits.insert(port(first, \Q)[slice]);
 	chain.emplace_back(first, slice);
 	subpattern(tail);
 finally