From: Luke Kenneth Casson Leighton Date: Tue, 7 Dec 2021 01:06:04 +0000 (+0000) Subject: submodule tidyup X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eea71fc1ed5cfce967580008da0bf9c97979de83;p=soc.git submodule tidyup --- diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 60e06c11..180fa10d 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1231,7 +1231,7 @@ class DCache(Elaboratable): d_out = Signal(WB_DATA_BITS, name="dout_%d" % i) # cache_row_t way = CacheRam(ROW_BITS, WB_DATA_BITS, ADD_BUF=True, ram_num=i) - setattr(m.submodules, "cacheram_%d" % i, way) + m.submodules["cacheram_%d" % i] = way comb += way.rd_en.eq(do_read) comb += way.rd_addr.eq(rd_addr)