From: lkcl <lkcl@web>
Date: Sun, 5 Jun 2022 19:04:14 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1938
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eea7504cc2f54fdd02be7558a2e4fbb8b7af184f;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 85df80a77..2a61fb58b 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -121,13 +121,28 @@ where bit 2 is inv, bits 0:1 select the bit of the CR.
         mask = get_src_predicate()
         count = 0
         for i in range(VL):
-            if mask & (1<<i) == 0: continue
+            if mask & (1<<i) == 0:
+                count = 0 # reset back to zero
+                continue
             iregs[RT+i] = count
             if test_CR_bit(CR[i+BA], BO):
                  count += 1
 
 the variant of iotacr which is vidcr, this is not appropriate to have BA=0, plus, it is pointless to have it anyway.  The integer version covers it, by not reading the int regfile at all.
 
+scalar variant which can be Vectorised to give iotacr:
+
+     def crtaddi(RT, RA, BA, BO, D): 
+         if test_CR_bit(BA, BO):
+             RT = RA + EXTS(D)
+         else:
+             RT = RA
+
+a Vector for-loop with zero-ing on dest will give the
+mask-out effect of resetting the count back to zero.
+However close examination shows that the above may actually
+be `sv.addi/mr/sm=EQ/dz r0.v, r0.v, 1` 
+
 # Scalar
 
 These may all be viewed as suitable for fitting into a scalar bitmanip extension.