From: lkcl <lkcl@web>
Date: Sun, 1 Aug 2021 10:40:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~554
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eeb6df96c4a50f34749d1a168d799a06ca4fcbbe;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 8764fb765..db56a0a16 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -764,17 +764,16 @@ def reduce(  vl,  vec, pred, pred,):
        if pbit:
            vi[j] = i
            j += 1
-    step = 1
-    while step < vl
-        step *= 2
+    step = 2
+    while step <= vl
+        halfstep = step // 2
         for i in (0..vl).step_by(step)
-            other = vi[i + step / 2]
+            other = vi[i + halfstep]
             i = vi[i]
             other_pred = other < vl && pred[other]
             if pred[i] && other_pred
                 vec[i] += vec[other]
             pred[i] |= other_pred
-
-
+         step *= 2
 
 ```