From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 22:14:41 +0000 (-0700)
Subject: Update fsm.ys resource count
X-Git-Tag: working-ls180~989^2~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eeb86247c59f7ea7f98c05eaa456d0ebe041d149;p=yosys.git

Update fsm.ys resource count
---

diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys
index bdd910163..36b10c0ce 100644
--- a/tests/ecp5/fsm.ys
+++ b/tests/ecp5/fsm.ys
@@ -8,7 +8,7 @@ equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:L6MUX21
-select -assert-count 15 t:LUT4
-select -assert-count 6 t:PFUMX
-select -assert-count 6 t:TRELLIS_FF
+select -assert-count 13 t:LUT4
+select -assert-count 5 t:PFUMX
+select -assert-count 5 t:TRELLIS_FF
 select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D