From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 17 Sep 2009 02:28:01 +0000 (-0700)
Subject: X86: Fix setting the busy bit in the task descriptor in LTR.
X-Git-Tag: stable_2012_02_02~1744
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eec6bfaa9de23b075762a62e57e46cd3f2f977ef;p=gem5.git

X86: Fix setting the busy bit in the task descriptor in LTR.
---

diff --git a/src/arch/x86/isa/insts/system/segmentation.py b/src/arch/x86/isa/insts/system/segmentation.py
index b83fcba95..c97f2f152 100644
--- a/src/arch/x86/isa/insts/system/segmentation.py
+++ b/src/arch/x86/isa/insts/system/segmentation.py
@@ -179,7 +179,8 @@ def macroop LTR_R
     wrdh t3, t1, t2
     wrdl tr, t1, reg
     wrbase tr, t3, dataSize=8
-    ori t1, t1, (1 << 9)
+    limm t5, (1 << 9)
+    or t1, t1, t5
     st t1, tsg, [8, t4, t0], dataSize=8
 };
 
@@ -195,7 +196,8 @@ def macroop LTR_M
     wrdh t3, t1, t2
     wrdl tr, t1, t5
     wrbase tr, t3, dataSize=8
-    ori t1, t1, (1 << 9)
+    limm t5, (1 << 9)
+    or t1, t1, t5
     st t1, tsg, [8, t4, t0], dataSize=8
 };
 
@@ -212,7 +214,8 @@ def macroop LTR_P
     wrdh t3, t1, t2
     wrdl tr, t1, t5
     wrbase tr, t3, dataSize=8
-    ori t1, t1, (1 << 9)
+    limm t5, (1 << 9)
+    or t1, t1, t5
     st t1, tsg, [8, t4, t0], dataSize=8
 };