From: Gabe Black Date: Tue, 5 Nov 2019 23:45:07 +0000 (-0800) Subject: fastmodel: Implement readVecRegFlat for ArmThreadContext. X-Git-Tag: v19.0.0.0~160 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eec8ac1595320cf40650f3c03f05248015dd17ae;p=gem5.git fastmodel: Implement readVecRegFlat for ArmThreadContext. This just calls readVecReg after constructing a RegId. Change-Id: Ia26b9bb874fec62f98bd5e4d3c6aa1059766c2f6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23783 Tested-by: kokoro Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini --- diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.cc b/src/arch/arm/fastmodel/iris/arm/thread_context.cc index 8a36ce3d3..c48ade817 100644 --- a/src/arch/arm/fastmodel/iris/arm/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/arm/thread_context.cc @@ -201,6 +201,12 @@ ArmThreadContext::readVecReg(const RegId ®_id) const return reg; } +const ArmISA::VecRegContainer & +ArmThreadContext::readVecRegFlat(RegIndex idx) const +{ + return readVecReg(RegId(VecRegClass, idx)); +} + Iris::ThreadContext::IdxNameMap ArmThreadContext::miscRegIdxNameMap({ { ArmISA::MISCREG_CPSR, "CPSR" }, { ArmISA::MISCREG_SPSR, "SPSR" }, diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.hh b/src/arch/arm/fastmodel/iris/arm/thread_context.hh index c7f26e3bd..8344f57b8 100644 --- a/src/arch/arm/fastmodel/iris/arm/thread_context.hh +++ b/src/arch/arm/fastmodel/iris/arm/thread_context.hh @@ -83,6 +83,7 @@ class ArmThreadContext : public Iris::ThreadContext } const VecRegContainer &readVecReg(const RegId ®) const override; + const VecRegContainer &readVecRegFlat(RegIndex idx) const override; }; } // namespace Iris