From: Cesar Strauss <cestrauss@gmail.com>
Date: Tue, 30 Mar 2021 11:21:09 +0000 (-0300)
Subject: Memory port seems to have been renamed
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eed32853f8109e85a7f460941c9185771010c137;p=soc.git

Memory port seems to have been renamed
---

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 41b5a76a..eb75d3b4 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -395,17 +395,17 @@ class TestRunner(FHDLTestCase):
             {'comment': 'instruction memory'},
             'imem.sram.rdport.memory(0)[63:0]',
             {'comment': 'registers'},
-            'core.int.rp_src1.memory(0)[63:0]',
-            'core.int.rp_src1.memory(1)[63:0]',
-            'core.int.rp_src1.memory(2)[63:0]',
-            'core.int.rp_src1.memory(3)[63:0]',
-            'core.int.rp_src1.memory(4)[63:0]',
-            'core.int.rp_src1.memory(5)[63:0]',
-            'core.int.rp_src1.memory(6)[63:0]',
-            'core.int.rp_src1.memory(7)[63:0]',
-            'core.int.rp_src1.memory(9)[63:0]',
-            'core.int.rp_src1.memory(10)[63:0]',
-            'core.int.rp_src1.memory(13)[63:0]',
+            'core.int.rp_src.memory(0)[63:0]',
+            'core.int.rp_src.memory(1)[63:0]',
+            'core.int.rp_src.memory(2)[63:0]',
+            'core.int.rp_src.memory(3)[63:0]',
+            'core.int.rp_src.memory(4)[63:0]',
+            'core.int.rp_src.memory(5)[63:0]',
+            'core.int.rp_src.memory(6)[63:0]',
+            'core.int.rp_src.memory(7)[63:0]',
+            'core.int.rp_src.memory(9)[63:0]',
+            'core.int.rp_src.memory(10)[63:0]',
+            'core.int.rp_src.memory(13)[63:0]',
         ]
 
         if self.microwatt_mmu: