From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 27 Jun 2021 12:52:25 +0000 (+0100)
Subject: add FRS decode (2nd output) for SVP64 FFT FP mul-add in PowerDecoder2
X-Git-Tag: xlen-bcd~366
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eed3e798cde19f89cc58be2b6b342d14d68951ba;p=openpower-isa.git

add FRS decode (2nd output) for SVP64 FFT FP mul-add in PowerDecoder2
---

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 92281019..e8f6cceb 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -449,6 +449,7 @@ class DecodeOut2(Elaboratable):
         self.dec = dec
         self.op = op
         self.sel_in = Signal(OutSel, reset_less=True)
+        self.svp64_fft_mode = Signal(reset_less=True) # SVP64 FFT mode
         self.lk = Signal(reset_less=True)
         self.insn_in = Signal(32, reset_less=True)
         self.reg_out = Data(5, "reg_o2")
@@ -487,6 +488,13 @@ class DecodeOut2(Elaboratable):
                 comb += self.fast_out3.data.eq(FastRegsEnum.SVSRR0) # SVSRR0
                 comb += self.fast_out3.ok.eq(1)
 
+            # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT
+            # will be offset by VL in hardware
+            with m.Case(MicrOp.OP_FP_MADD):
+                with m.If(self.svp64_fft_mode):
+                    comb += self.reg_out.data.eq(self.dec.FRT)
+                    comb += self.reg_out.ok.eq(1)
+
         return m
 
 
@@ -1194,6 +1202,8 @@ class PowerDecode2(PowerDecodeSubset):
         comb += dec_c.sel_in.eq(self.op_get("in3_sel"))
         comb += dec_o.sel_in.eq(self.op_get("out_sel"))
         comb += dec_o2.sel_in.eq(self.op_get("out_sel"))
+        if self.svp64_en:
+            comb += dec_o2.svp64_fft_mode.eq(self.use_svp64_fft)
         if hasattr(do, "lk"):
             comb += dec_o2.lk.eq(do.lk)