From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 10 May 2021 23:43:17 +0000 (+0100)
Subject: add block for MMU activation to LoadStore1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eee4ddc3b148e320f9310091ffa0ea84130918ca;p=soc.git

add block for MMU activation to LoadStore1
---

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 6035fee5..2107cda6 100644
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -181,6 +181,10 @@ class LoadStore1(PortInterfaceBase):
         # temp vars
         d_in, d_out, l_out, dbus = self.d_in, self.d_out, self.l_out, self.dbus
 
+        # copy of address, but gets over-ridden for OP_FETCH_FAILED
+        maddr = Signal(64)
+        m.d.comb += maddr.eq(self.addr)
+
         # create a blip (single pulse) on valid read/write request
         # this can be over-ridden in the FSM to get dcache to re-run
         # a request when MMU_LOOKUP completes
@@ -206,7 +210,7 @@ class LoadStore1(PortInterfaceBase):
                         # Look up the translation for TLB miss
                         # and also for permission error and RC error
                         # in case the PTE has been updated.
-                        sync += self.mmureq.eq(1)
+                        comb += self.mmureq.eq(1)
                         sync += self.state.eq(State.MMU_LOOKUP)
                 with m.If(d_out.valid):
                     m.d.comb += self.done.eq(1)
@@ -301,6 +305,20 @@ class LoadStore1(PortInterfaceBase):
         m.d.comb += self.done.eq(d_out.valid)
         m.d.comb += self.load_data.eq(d_out.data)
 
+        ''' TODO: translate to nmigen.
+        -- Update outputs to MMU
+        m_out.valid <= mmureq;
+        m_out.iside <= v.instr_fault;
+        m_out.load <= r.load;
+        # m_out.priv <= r.priv_mode; TODO
+        m_out.tlbie <= v.tlbie;
+        # m_out.mtspr <= mmu_mtspr; # TODO
+        # m_out.sprn <= sprn; # TODO
+        m_out.addr <= maddr;
+        # m_out.slbia <= l_in.insn(7); # TODO: no idea what this is
+        # m_out.rs <= l_in.data; # nope, probably not needed, TODO investigate
+        '''
+
         return m
 
     def ports(self):
diff --git a/src/soc/simple/test/test_issuer_mmu.py b/src/soc/simple/test/test_issuer_mmu.py
index 4bf4d37a..b24b73eb 100644
--- a/src/soc/simple/test/test_issuer_mmu.py
+++ b/src/soc/simple/test/test_issuer_mmu.py
@@ -46,12 +46,12 @@ if __name__ == "__main__":
     #                          microwatt_mmu=True))
 
     # LD/ST tests should all still work
-    suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64,
-                              microwatt_mmu=True))
+    #suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64,
+    #                          microwatt_mmu=True))
 
     # LD/ST exception cases
-    #suite.addTest(TestRunner(LDSTExceptionTestCase().test_data, svp64=svp64,
-    #                          microwatt_mmu=True))
+    suite.addTest(TestRunner(LDSTExceptionTestCase().test_data, svp64=svp64,
+                              microwatt_mmu=True))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)