From: Giacomo Gabrielli Date: Wed, 2 Oct 2019 14:43:47 +0000 (+0100) Subject: cpu-o3: Fix handling of some mem. order violations X-Git-Tag: v19.0.0.0~365 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eef524d9ecf692875c899f112c4ddfdec03d7088;p=gem5.git cpu-o3: Fix handling of some mem. order violations This patch fixes the handling of memory order violations due to snoops targeting out-of-order loads: the re-execution triggered in these cases is achieved by raising a ReExec fault, but such a fault was not handled correctly after the code changes introduced in changeset 46da8fb. Change-Id: I2abe161a90468412f56cb28dcc92729326cba1cd Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21819 Tested-by: kokoro Reviewed-by: Timothy Hayes Reviewed-by: Brandon Potter Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index 6225c507d..ca92790b8 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012, 2014, 2018 ARM Limited + * Copyright (c) 2011-2012, 2014, 2018-2019 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -623,6 +623,12 @@ class LSQ (isPartialFault() && isLoad())); } + void + setStateToFault() + { + setState(State::Fault); + } + /** * The LSQ entry is cleared */ diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index c2483d567..553c903e7 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -1,6 +1,6 @@ /* - * Copyright (c) 2010-2014, 2017-2018 ARM Limited + * Copyright (c) 2010-2014, 2017-2019 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -426,6 +426,7 @@ LSQUnit::checkSnoop(PacketPtr pkt) // Mark the load for re-execution ld_inst->fault = std::make_shared(); + req->setStateToFault(); } else { DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n", pkt->getAddr(), ld_inst->seqNum);