From: Andrew Cagney Date: Wed, 11 Mar 1998 12:18:39 +0000 (+0000) Subject: Allow more than just read, write and exec memory spaces in the core X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eefc25e592ff4681d6a9806e43cd2fc432721ccb;p=binutils-gdb.git Allow more than just read, write and exec memory spaces in the core module. --- diff --git a/sim/common/sim-break.c b/sim/common/sim-break.c index d40d35bb63e..07d1f954e83 100644 --- a/sim/common/sim-break.c +++ b/sim/common/sim-break.c @@ -52,7 +52,8 @@ static SIM_RC resume_handler PARAMS ((SIM_DESC sd)); static SIM_RC suspend_handler PARAMS ((SIM_DESC sd)); -/* Do the actual work of inserting a breakpoint into the instruction stream. */ +/* Do the actual work of inserting a breakpoint into the instruction + stream. */ static void insert_breakpoint (sd, bp) @@ -62,9 +63,9 @@ insert_breakpoint (sd, bp) if (bp->flags & (SIM_BREAK_INSERTED | SIM_BREAK_DISABLED)) return; - sim_core_read_buffer (sd, NULL, sim_core_write_map, bp->loc_contents, + sim_core_read_buffer (sd, NULL, exec_map, bp->loc_contents, bp->addr, SIM_BREAKPOINT_SIZE); - sim_core_write_buffer (sd, NULL, sim_core_write_map, sim_breakpoint, + sim_core_write_buffer (sd, NULL, exec_map, sim_breakpoint, bp->addr, SIM_BREAKPOINT_SIZE); bp->flags |= SIM_BREAK_INSERTED; } @@ -79,7 +80,7 @@ remove_breakpoint (sd, bp) if (!(bp->flags & SIM_BREAK_INSERTED)) return; - sim_core_write_buffer (sd, NULL, sim_core_write_map, bp->loc_contents, + sim_core_write_buffer (sd, NULL, exec_map, bp->loc_contents, bp->addr, SIM_BREAKPOINT_SIZE); bp->flags &= SIM_BREAK_INSERTED; } diff --git a/sim/mips/sky-pke.h b/sim/mips/sky-pke.h index 8244ee5380f..d8b489e6a71 100644 --- a/sim/mips/sky-pke.h +++ b/sim/mips/sky-pke.h @@ -408,7 +408,7 @@ struct pke_device do { \ sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \ unsigned_##size value = \ - sim_core_read_aligned_##size(cpu, CIA_GET(cpu), sim_core_read_map, \ + sim_core_read_aligned_##size(cpu, CIA_GET(cpu), read_map, \ (SIM_ADDR)(addr)); \ memcpy((unsigned_##size*) (data), (void*) & value, size); \ } while(0) @@ -417,7 +417,7 @@ struct pke_device do { sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \ unsigned_##size value; \ memcpy((void*) & value, (unsigned_##size*)(data), size); \ - sim_core_write_aligned_##size(cpu, CIA_GET(cpu), sim_core_write_map, \ + sim_core_write_aligned_##size(cpu, CIA_GET(cpu), write_map, \ (SIM_ADDR)(addr), value); \ if((me)->fifo_trace_file != NULL) \ { \ diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog index 4ab9129f709..777ed7e152f 100644 --- a/sim/tic80/ChangeLog +++ b/sim/tic80/ChangeLog @@ -1,3 +1,8 @@ +Wed Mar 11 14:12:56 1998 Andrew Cagney + + * alu.h (IMEM32_IMMED, IMEM32, STORE, MEM): Replace sim_core_*_map + with read_map, write_map, exec_map resp. + Thu Feb 26 19:08:37 1998 Andrew Cagney * sim-calls.c (sim_info): Delete. diff --git a/sim/tic80/alu.h b/sim/tic80/alu.h index 4def0ee2391..b5bc7c1af31 100644 --- a/sim/tic80/alu.h +++ b/sim/tic80/alu.h @@ -39,20 +39,20 @@ with this program; if not, write to the Free Software Foundation, Inc., /* Bring data in from the cold */ #define IMEM32(CIA) \ -(sim_core_read_aligned_4(STATE_CPU (sd, 0), CIA, sim_core_execute_map, (CIA).ip)) +(sim_core_read_aligned_4(STATE_CPU (sd, 0), CIA, exec_map, (CIA).ip)) #define IMEM32_IMMED(CIA, N) \ -(sim_core_read_aligned_4 (STATE_CPU (sd, 0), CIA, sim_core_execute_map, (CIA).ip + 4 * (N))) +(sim_core_read_aligned_4 (STATE_CPU (sd, 0), CIA, exec_map, (CIA).ip + 4 * (N))) #define MEM(SIGN, EA, NR_BYTES) \ ((SIGN##_##NR_BYTES) sim_core_read_unaligned_##NR_BYTES (STATE_CPU (sd, 0), cia, \ - sim_core_read_map, \ + read_map, \ (EA))) #define STORE(EA, NR_BYTES, VAL) \ do { \ sim_core_write_unaligned_##NR_BYTES (STATE_CPU (sd, 0), cia, \ - sim_core_write_map, \ + write_map, \ (EA), (VAL)); \ } while (0) diff --git a/sim/txvu/ChangeLog b/sim/txvu/ChangeLog index c053a248e72..bc93449d5ad 100644 --- a/sim/txvu/ChangeLog +++ b/sim/txvu/ChangeLog @@ -1,3 +1,8 @@ +Wed Mar 11 14:14:02 1998 Andrew Cagney + + * interp.c (sim_write, sim_read, load_memory, store_memory): + Replace sim_core_*_map with read_map, write_map, exec_map resp. + Tue Jan 27 18:24:01 1998 Ian Carmichael * Very, very early support for vu1 based on sce code. diff --git a/sim/txvu/interp.c b/sim/txvu/interp.c index 52fba47c0c1..5fc22d2cb15 100644 --- a/sim/txvu/interp.c +++ b/sim/txvu/interp.c @@ -510,7 +510,7 @@ sim_write (sd,addr,buffer,size) int cca; if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW)) break; - if (sim_core_write_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1) + if (sim_core_write_buffer (sd, NULL, read_map, buffer + index, paddr, 1) != 1) break; } @@ -538,7 +538,7 @@ sim_read (sd,addr,buffer,size) int cca; if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW)) break; - if (sim_core_read_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1) + if (sim_core_read_buffer (sd, NULL, read_map, buffer + index, paddr, 1) != 1) break; } @@ -1352,39 +1352,38 @@ load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD) { case AccessLength_QUADWORD : { - unsigned_16 val = sim_core_read_aligned_16 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_read_map, pAddr); + unsigned_16 val = sim_core_read_aligned_16 (STATE_CPU (sd, 0), NULL_CIA, read_map, pAddr); value1 = VH8_16 (val); value = VL8_16 (val); break; } case AccessLength_DOUBLEWORD : value = sim_core_read_aligned_8 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); break; case AccessLength_SEPTIBYTE : value = sim_core_read_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); case AccessLength_SEXTIBYTE : value = sim_core_read_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); case AccessLength_QUINTIBYTE : value = sim_core_read_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); case AccessLength_WORD : value = sim_core_read_aligned_4 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); break; case AccessLength_TRIPLEBYTE : value = sim_core_read_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); case AccessLength_HALFWORD : value = sim_core_read_aligned_2 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); break; case AccessLength_BYTE : value = sim_core_read_aligned_1 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); break; default: abort (); @@ -1485,40 +1484,40 @@ store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr) { unsigned_16 val = U16_8 (MemElem1, MemElem); sim_core_write_aligned_16 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_write_map, pAddr, val); + write_map, pAddr, val); break; } case AccessLength_DOUBLEWORD : sim_core_write_aligned_8 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_SEPTIBYTE : sim_core_write_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_SEXTIBYTE : sim_core_write_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_QUINTIBYTE : sim_core_write_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_WORD : sim_core_write_aligned_4 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_TRIPLEBYTE : sim_core_write_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_HALFWORD : sim_core_write_aligned_2 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_BYTE : sim_core_write_aligned_1 (STATE_CPU (sd, 0), NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; default: abort ();