From: lkcl <lkcl@web>
Date: Fri, 8 Jan 2021 14:29:13 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~553
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef01e253378b20537907c7e2f5f7b7cb89aaec65;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index f4b306f11..457d96ded 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -34,8 +34,8 @@ At the minimum however it is possible to provide unit stride and vector mode, as
     # LD not VLD!
     # op_width: lb=1, lh=2, lw=4, ld=8
     op_load(RT, RA, op_width, immed, svctx, update):
-      rdv = map_dest_extra(RT);
-      rsv = map_src_extra(RA);
+      rdv = map_dest_extra(RT); # possible REMAP
+      rsv = map_src_extra(RA);  # possible REMAP
       ps = get_pred_val(FALSE, RA); # predication on src
       pd = get_pred_val(FALSE, RT); # ... AND on dest
       for (int i = 0, int j = 0; i < VL && j < VL;):
@@ -44,28 +44,27 @@ At the minimum however it is possible to provide unit stride and vector mode, as
         if (RT.isvec) while (!(pd & 1<<j)) j++;
         if RA.isvec:
           # indirect mode (multi mode)
-          EA = ireg[rsv+i] + immed;
-          if update: ireg[rsv+i] = EA;
-        elif svctx.ldstmode == elementstride:
-          # element stride mode
-          EA = ireg[rsv] + i * immed
-          # note: overwrites repeatedly, effectively
-          # giving the last non-masked-out value 
-          if update: ireg[rsv] = EA;
-        elif svctx.ldstmode == unitstride:
-          # unit and element stride mode
-          EA = ireg[rsv] + i * op_width
-          # note: overwrites repeatedly, effectively
-          # giving the last non-masked-out value 
-          if update: ireg[rsv] = EA;
-        else
-          # standard scalar mode (but predicated)
-          # no stride multiplier means VSPLAT/VINSERT mode
-          EA = ireg[rsv] + immed
-          if update: ireg[rsv] = EA;
+          srcbase = ireg[RA+i]
+          offs = immed;
+        else:
+          srcbase = ireg[RA]
+          if svctx.ldstmode == elementstride:
+            # element stride mode
+            offs = i * immed
+          elif svctx.ldstmode == unitstride:
+            # unit stride mode
+            offs = i * op_width
+          else
+            # standard scalar mode (but predicated)
+            # no stride multiplier means VSPLAT mode
+            offs = immed
+        # compute EA
+        EA = srcbase + offs
+        # update RA? load from memory
+        if update: ireg[rsv+i] = EA;
         ireg[rdv+j] <= MEM[EA];
         if (!RT.isvec)
-            break # destination scalar, end immediately
+            break # destination scalar, end now
         if (RA.isvec) i++;
         if (RT.isvec) j++;