From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Sep 2019 15:43:22 +0000 (-0700)
Subject: simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select
X-Git-Tag: working-ls180~1058^2~15
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef0681ea4ca0b34689cbf14d5a4478e2785600d9;p=yosys.git

simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select
---

diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v
deleted file mode 100644
index b4d113dba..000000000
--- a/tests/simple/peepopt.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
-assign o = i[s*W+:W];
-endmodule
-
-module peepopt_shiftmul_1 (output y, input [2:0] w);
-assign y = 1'b1 >> (w * (3'b110));
-endmodule
-
-module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
-wire [3:0] t;
-assign t = i * 3;
-assign o = t / 3;
-endmodule
-
-module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
-    always @(posedge clk) if (ce) o <= i;
-endmodule
-
-module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o);
-    always @(posedge clk) if (ce) o <= i;
-endmodule
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
new file mode 100644
index 000000000..91db22423
--- /dev/null
+++ b/tests/various/peepopt.ys
@@ -0,0 +1,63 @@
+read_verilog <<EOT
+module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
+assign o = i[s*W+:W];
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt peepopt
+design -load postopt
+clean
+select -assert-count 1 t:$shiftx
+select -assert-count 0 t:$shiftx t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
+assign y = 1'b1 >> (w * (3'b110));
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt peepopt
+design -load postopt
+clean
+select -assert-count 1 t:$shr
+select -assert-count 1 t:$mul
+select -assert-count 0 t:$shr t:$mul %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
+wire [3:0] t;
+assign t = i * 3;
+assign o = t / 3;
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt peepopt
+design -load postopt
+clean
+select -assert-count 0 t:*
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
+    always @(posedge clk) if (ce) o <= i;
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt peepopt
+design -load postopt
+clean
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 1 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$dff t:$mux %% t:* %D