From: lkcl Date: Sat, 23 Jul 2022 10:47:55 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~1097 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef0a83e4d3684c2e5a1442ea3c59f05fb912f70c;p=libreriscv.git --- diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn index a82cc5362..7ff6d1f51 100644 --- a/openpower/sv/executive_summary.mdwn +++ b/openpower/sv/executive_summary.mdwn @@ -1,4 +1,12 @@ -Simple-V is a Scalable Vector ISA Extension specifically for the Power ISA. +Simple-V is a Scalable Vector ISA Extension specifically tailored +for the uniquely powerful capabilities of the Power ISA. + +**Simple-V does not modify harm or corrupt the existing Power ISA** and +does not interfere with an existing system. It needs only a small +allocation of opcodes (five) to implement, whereas any other Vector +implementation would require an intrusive fundamental overhaul of the +Power ISA. + It is extremely important to think of Simple-V as a 2-Dimensional ISA: instructions vertical and registers horizontal otherwise it will be difficult to understand. @@ -14,10 +22,6 @@ ARM NEON, AVX-512 and ARM SVE2 are all Predicated SIMD ISAs and through explicit predicate masks which increases instruction count in hot-loops. -**Simple-V does not modify harm or corrupt the existing Power ISA** and does not -interfere with an existing system. It needs only a small allocation of opcodes (five) to implement, whereas any other Vector implementation would -require an intrusive fundamental overhaul of the Power ISA. - We invented Simple-V to be simple because we don't like complicated. Links to Simulator, installation scripts, and Unit tests: