From: Luke Kenneth Casson Leighton Date: Sat, 9 Mar 2019 09:13:47 +0000 (+0000) Subject: big reorganisation X-Git-Tag: ls180-24jan2020~1715 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef144a6f35cf7d9bfc0268d50f1572be1ddf2e13;p=ieee754fpu.git big reorganisation splitting out Normalisation Single/Multi adding beginnings of combinatorial-chained normalisation thru pack --- diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index f32b3777..ed04deae 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -664,15 +664,22 @@ class FPNorm1ModSingle: def __init__(self, width): self.width = width - self.in_select = Signal(reset_less=True) self.out_norm = Signal(reset_less=True) self.in_z = FPNumBase(width, False) self.in_of = Overflow() - self.temp_z = FPNumBase(width, False) - self.temp_of = Overflow() self.out_z = FPNumBase(width, False) self.out_of = Overflow() + def setup(self, m, in_z, in_of, out_z): + """ links module to inputs and outputs + """ + m.submodules.normalise_1 = self + + m.d.comb += self.in_z.copy(in_z) + m.d.comb += self.in_of.copy(in_of) + + m.d.comb += out_z.copy(self.out_z) + def elaborate(self, platform): m = Module() @@ -682,8 +689,6 @@ class FPNorm1ModSingle: m.submodules.norm1_out_z = self.out_z m.submodules.norm1_out_overflow = self.out_of - m.submodules.norm1_temp_z = self.temp_z - m.submodules.norm1_temp_of = self.temp_of m.submodules.norm1_in_z = self.in_z m.submodules.norm1_in_overflow = self.in_of @@ -697,13 +702,8 @@ class FPNorm1ModSingle: msr = MultiShiftRMerge(mwid, espec) m.submodules.multishift_r = msr - # select which of temp or in z/of to use - with m.If(self.in_select): - m.d.comb += in_z.copy(self.in_z) - m.d.comb += in_of.copy(self.in_of) - with m.Else(): - m.d.comb += in_z.copy(self.temp_z) - m.d.comb += in_of.copy(self.temp_of) + m.d.comb += in_z.copy(self.in_z) + m.d.comb += in_of.copy(self.in_of) # initialise out from in (overridden below) m.d.comb += self.out_z.copy(in_z) m.d.comb += self.out_of.copy(in_of) @@ -712,7 +712,6 @@ class FPNorm1ModSingle: increase = Signal(reset_less=True) m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126) m.d.comb += increase.eq(in_z.exp_lt_n126) - m.d.comb += self.out_norm.eq(0) # loop-end condition # decrease exponent with m.If(decrease): # *sigh* not entirely obvious: count leading zeros (clz) @@ -828,15 +827,36 @@ class FPNorm1ModMulti: return m -class FPNorm1(FPState, FPID): +class FPNorm1Single(FPState, FPID): def __init__(self, width, id_wid, single_cycle=True): FPID.__init__(self, id_wid) FPState.__init__(self, "normalise_1") - if single_cycle: - self.mod = FPNorm1ModSingle(width) - else: - self.mod = FPNorm1ModMulti(width) + self.mod = FPNorm1ModSingle(width) + self.out_norm = Signal(reset_less=True) + self.out_z = FPNumBase(width) + self.out_roundz = Signal(reset_less=True) + + def setup(self, m, in_z, in_of, in_mid): + """ links module to inputs and outputs + """ + self.mod.setup(m, in_z, in_of, self.out_z) + + if self.in_mid is not None: + m.d.comb += self.in_mid.eq(in_mid) + + def action(self, m): + self.idsync(m) + m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz) + m.next = "round" + + +class FPNorm1Multi(FPState, FPID): + + def __init__(self, width, id_wid): + FPID.__init__(self, id_wid) + FPState.__init__(self, "normalise_1") + self.mod = FPNorm1ModMulti(width) self.stb = Signal(reset_less=True) self.ack = Signal(reset=0, reset_less=True) self.out_norm = Signal(reset_less=True) @@ -849,17 +869,64 @@ class FPNorm1(FPState, FPID): def setup(self, m, in_z, in_of, norm_stb, in_mid): """ links module to inputs and outputs """ - m.submodules.normalise_1 = self.mod + self.mod.setup(m, in_z, in_of, norm_stb, + self.in_accept, self.temp_z, self.temp_of, + self.out_z, self.out_norm) - m.d.comb += self.mod.in_z.copy(in_z) - m.d.comb += self.mod.in_of.copy(in_of) + m.d.comb += self.stb.eq(norm_stb) + m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state - m.d.comb += self.mod.in_select.eq(self.in_accept) - m.d.comb += self.mod.temp_z.copy(self.temp_z) - m.d.comb += self.mod.temp_of.copy(self.temp_of) + if self.in_mid is not None: + m.d.comb += self.in_mid.eq(in_mid) - m.d.comb += self.out_z.copy(self.mod.out_z) - m.d.comb += self.out_norm.eq(self.mod.out_norm) + def action(self, m): + self.idsync(m) + m.d.comb += self.in_accept.eq((~self.ack) & (self.stb)) + m.d.sync += self.temp_of.copy(self.mod.out_of) + m.d.sync += self.temp_z.copy(self.out_z) + with m.If(self.out_norm): + with m.If(self.in_accept): + m.d.sync += [ + self.ack.eq(1), + ] + with m.Else(): + m.d.sync += self.ack.eq(0) + with m.Else(): + # normalisation not required (or done). + m.next = "round" + m.d.sync += self.ack.eq(1) + m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz) + + +class FPNorm1ToPack(FPState, FPID): + + def __init__(self, width, id_wid, single_cycle=True): + FPID.__init__(self, id_wid) + FPState.__init__(self, "normalise_1") + if single_cycle: + self.mod = FPNorm1ModSingle(width) + else: + self.mod = FPNorm1ModMulti(width) + self.mod = FPNorm1ModMulti(width) + self.stb = Signal(reset_less=True) + self.ack = Signal(reset=0, reset_less=True) + self.out_norm = Signal(reset_less=True) + self.in_accept = Signal(reset_less=True) + self.temp_z = FPNumBase(width) + self.temp_of = Overflow() + self.n_out_z = FPNumBase(width) + self.n_out_roundz = Signal(reset_less=True) + + self.rmod = FPRoundMod(width) + self.out_z = FPNumBase(width) + self.rmod.setup(m, self.n_out_z, self.n_out_roundz) + + def setup(self, m, in_z, in_of, norm_stb, in_mid): + """ links module to inputs and outputs + """ + self.mod.setup(m, in_z, in_of, norm_stb, + self.in_accept, self.temp_z, self.temp_of, + self.n_out_z, self.out_norm) m.d.comb += self.stb.eq(norm_stb) m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state @@ -871,7 +938,7 @@ class FPNorm1(FPState, FPID): self.idsync(m) m.d.comb += self.in_accept.eq((~self.ack) & (self.stb)) m.d.sync += self.temp_of.copy(self.mod.out_of) - m.d.sync += self.temp_z.copy(self.out_z) + m.d.sync += self.temp_z.copy(self.n_out_z) with m.If(self.out_norm): with m.If(self.in_accept): m.d.sync += [ @@ -883,7 +950,7 @@ class FPNorm1(FPState, FPID): # normalisation not required (or done). m.next = "round" m.d.sync += self.ack.eq(1) - m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz) + m.d.sync += self.n_out_roundz.eq(self.mod.out_of.roundz) class FPRoundMod: @@ -893,6 +960,12 @@ class FPRoundMod: self.in_z = FPNumBase(width, False) self.out_z = FPNumBase(width, False) + def setup(self, m, in_z, roundz): + m.submodules.roundz = self + + m.d.comb += self.in_z.copy(in_z) + m.d.comb += self.in_roundz.eq(roundz) + def elaborate(self, platform): m = Module() m.d.comb += self.out_z.copy(self.in_z) @@ -914,10 +987,8 @@ class FPRound(FPState, FPID): def setup(self, m, in_z, roundz, in_mid): """ links module to inputs and outputs """ - m.submodules.roundz = self.mod + self.mod.setup(m, in_z, roundz) - m.d.comb += self.mod.in_z.copy(in_z) - m.d.comb += self.mod.in_roundz.eq(roundz) if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) @@ -1027,7 +1098,7 @@ class FPPutZ(FPState): class FPADDBaseMod(FPID): - def __init__(self, width, id_wid=None, single_cycle=False, compact=True): + def __init__(self, width, id_wid=None, single_cycle=False, compact=False): """ IEEE754 FP Add * width: bit-width of IEEE754. supported: 16, 32, 64 @@ -1097,8 +1168,12 @@ class FPADDBaseMod(FPID): add1 = self.add_state(FPAddStage1(self.width, self.id_wid)) add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid) - n1 = self.add_state(FPNorm1(self.width, self.id_wid)) - n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid) + if self.single_cycle: + n1 = self.add_state(FPNorm1Single(self.width, self.id_wid)) + n1.setup(m, add1.out_z, add1.out_of, add0.in_mid) + else: + n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid)) + n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid) rn = self.add_state(FPRound(self.width, self.id_wid)) rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid) @@ -1142,14 +1217,11 @@ class FPADDBaseMod(FPID): add1 = self.add_state(FPAddStage1(self.width, self.id_wid)) add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid) - n1 = self.add_state(FPNorm1(self.width, self.id_wid)) + n1 = self.add_state(FPNormToPack(self.width, self.id_wid)) n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid) - rn = self.add_state(FPRound(self.width, self.id_wid)) - rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid) - cor = self.add_state(FPCorrections(self.width, self.id_wid)) - cor.setup(m, rn.out_z, rn.in_mid) + cor.setup(m, n1.out_z, rn.in_mid) pa = self.add_state(FPPack(self.width, self.id_wid)) pa.setup(m, cor.out_z, rn.in_mid)