From: Antia Puentes <apuentes@igalia.com>
Date: Tue, 16 Jun 2015 20:30:16 +0000 (+0200)
Subject: i965/nir/vec4: Prepare source and destination registers for ALU operations
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef1b30ae637e613b384541324c199d2dbe6b44bd;p=mesa.git

i965/nir/vec4: Prepare source and destination registers for ALU operations

This patch resolves and initializes the destination and the source
registers that are common to most ALU operations.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index bc5ebbea98e..46bfd3b81d9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -646,10 +646,27 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
    }
 }
 
+static unsigned
+brw_swizzle_for_nir_swizzle(uint8_t swizzle[4])
+{
+   return BRW_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
+}
+
 void
 vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
 {
-   /* @TODO: Not yet implemented */
+   dst_reg dst = get_nir_dest(instr->dest.dest,
+                              nir_op_infos[instr->op].output_type);
+   dst.writemask = instr->dest.write_mask;
+
+   src_reg op[4];
+   for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
+      op[i] = get_nir_src(instr->src[i].src,
+                          nir_op_infos[instr->op].input_types[i], 4);
+      op[i].swizzle = brw_swizzle_for_nir_swizzle(instr->src[i].swizzle);
+      op[i].abs = instr->src[i].abs;
+      op[i].negate = instr->src[i].negate;
+   }
 }
 
 void