From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 25 Sep 2023 21:41:49 +0000 (-0700)
Subject: format src/openpower/decoder/isa/test_mem.py
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef22973ee57cdd9a302284ff5a7d911df6074ff4;p=openpower-isa.git

format src/openpower/decoder/isa/test_mem.py
---

diff --git a/src/openpower/decoder/isa/test_mem.py b/src/openpower/decoder/isa/test_mem.py
index 39e7d0b8..30f0965d 100644
--- a/src/openpower/decoder/isa/test_mem.py
+++ b/src/openpower/decoder/isa/test_mem.py
@@ -8,26 +8,25 @@ from openpower.util import log
 
 
 class TestMem(unittest.TestCase):
-
     def test_mem_align_st(self):
         m = Mem(row_bytes=8, initial_mem={})
         m.st(4, 0x12345678, width=4, swap=False)
         d = m.dump()
-        log ("dict", d)
+        log("dict", d)
         self.assertEqual(d, [(0, 0x1234567800000000)])
 
     def test_mem_misalign_st(self):
         m = Mem(row_bytes=8, initial_mem={}, misaligned_ok=True)
         m.st(3, 0x12345678, width=4, swap=False)
         d = m.dump()
-        log ("dict", d)
+        log("dict", d)
         self.assertEqual(d, [(0, 0x0012345678000000)])
 
     def test_mem_misalign_st_rollover(self):
         m = Mem(row_bytes=8, initial_mem={}, misaligned_ok=True)
         m.st(6, 0x912345678, width=8, swap=False)
         d = m.dump()
-        log ("dict", d)
+        log("dict", d)
         self.assertEqual(d, [(0, 0x5678000000000000),
                              (8, 0x0000000000091234)])