From: Segher Boessenkool <segher@kernel.crashing.org>
Date: Fri, 9 Aug 2019 17:33:25 +0000 (+0200)
Subject: rs6000: vec-rotate-*.c fixes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef4ddda8c217b6ef41dabf828c580760921a5cfe;p=gcc.git

rs6000: vec-rotate-*.c fixes

This fixes two minor problems with the new testcases.  The first is
that almost all other tests, including all vec* tests, for powerpc use
names with dashes, not underscores.  The more important one is the the
vec-rotate-1.c and vec-rotate-3.c tests need the -maltivec flag.


gcc/testsuite/
	* gcc.target/powerpc/vec_rotate-1.c: Rename to ...
	* gcc.target/powerpc/vec-rotate-1.c: ... this.  Add -maltivec option.
	* gcc.target/powerpc/vec_rotate-2.c: Rename to ...
	* gcc.target/powerpc/vec-rotate-2.c: ... this.
	* gcc.target/powerpc/vec_rotate-3.c: Rename to ...
	* gcc.target/powerpc/vec-rotate-3.c: ... this.  Add -maltivec option.
	* gcc.target/powerpc/vec_rotate-4.c: Rename to ...
	* gcc.target/powerpc/vec-rotate-4.c: ... this.

From-SVN: r274239
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 51d0a87730b..7b2ce9057e9 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2019-08-09  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* gcc.target/powerpc/vec_rotate-1.c: Rename to ...
+	* gcc.target/powerpc/vec-rotate-1.c: ... this.  Add -maltivec option.
+	* gcc.target/powerpc/vec_rotate-2.c: Rename to ...
+	* gcc.target/powerpc/vec-rotate-2.c: ... this.
+	* gcc.target/powerpc/vec_rotate-3.c: Rename to ...
+	* gcc.target/powerpc/vec-rotate-3.c: ... this.  Add -maltivec option.
+	* gcc.target/powerpc/vec_rotate-4.c: Rename to ...
+	* gcc.target/powerpc/vec-rotate-4.c: ... this.
+
 2019-08-09  Sam Tebbs <sam.tebbs@arm.com>
 
 	* lib/target-supports.exp
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-rotate-1.c b/gcc/testsuite/gcc.target/powerpc/vec-rotate-1.c
new file mode 100644
index 00000000000..6fe96272dde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-rotate-1.c
@@ -0,0 +1,39 @@
+/* { dg-options "-O3 -maltivec" } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+
+/* Check vectorizer can exploit vector rotation instructions on Power, mainly
+   for the case rotation count is const number.
+
+   Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */
+
+#define N 256
+unsigned int suw[N], ruw[N];
+unsigned short suh[N], ruh[N];
+unsigned char sub[N], rub[N];
+
+void
+testUW ()
+{
+  for (int i = 0; i < 256; ++i)
+    ruw[i] = (suw[i] >> 8) | (suw[i] << (sizeof (suw[0]) * 8 - 8));
+}
+
+void
+testUH ()
+{
+  for (int i = 0; i < 256; ++i)
+    ruh[i] = (unsigned short) (suh[i] >> 9)
+	     | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - 9));
+}
+
+void
+testUB ()
+{
+  for (int i = 0; i < 256; ++i)
+    rub[i] = (unsigned char) (sub[i] >> 5)
+	     | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - 5));
+}
+
+/* { dg-final { scan-assembler {\mvrlw\M} } } */
+/* { dg-final { scan-assembler {\mvrlh\M} } } */
+/* { dg-final { scan-assembler {\mvrlb\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-rotate-2.c b/gcc/testsuite/gcc.target/powerpc/vec-rotate-2.c
new file mode 100644
index 00000000000..23598958ef2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-rotate-2.c
@@ -0,0 +1,18 @@
+/* { dg-options "-O3 -mdejagnu-cpu=power8" } */
+
+/* Check vectorizer can exploit vector rotation instructions on Power8, mainly
+   for the case rotation count is const number.
+
+   Check for vrld which is available on Power8 and above.  */
+
+#define N 256
+unsigned long long sud[N], rud[N];
+
+void
+testULL ()
+{
+  for (int i = 0; i < 256; ++i)
+    rud[i] = (sud[i] >> 8) | (sud[i] << (sizeof (sud[0]) * 8 - 8));
+}
+
+/* { dg-final { scan-assembler {\mvrld\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-rotate-3.c b/gcc/testsuite/gcc.target/powerpc/vec-rotate-3.c
new file mode 100644
index 00000000000..373056256fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-rotate-3.c
@@ -0,0 +1,40 @@
+/* { dg-options "-O3 -maltivec" } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+
+/* Check vectorizer can exploit vector rotation instructions on Power, mainly
+   for the case rotation count isn't const number.
+
+   Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */
+
+#define N 256
+unsigned int suw[N], ruw[N];
+unsigned short suh[N], ruh[N];
+unsigned char sub[N], rub[N];
+extern unsigned char rot_cnt;
+
+void
+testUW ()
+{
+  for (int i = 0; i < 256; ++i)
+    ruw[i] = (suw[i] >> rot_cnt) | (suw[i] << (sizeof (suw[0]) * 8 - rot_cnt));
+}
+
+void
+testUH ()
+{
+  for (int i = 0; i < 256; ++i)
+    ruh[i] = (unsigned short) (suh[i] >> rot_cnt)
+	     | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - rot_cnt));
+}
+
+void
+testUB ()
+{
+  for (int i = 0; i < 256; ++i)
+    rub[i] = (unsigned char) (sub[i] >> rot_cnt)
+	     | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - rot_cnt));
+}
+
+/* { dg-final { scan-assembler {\mvrlw\M} } } */
+/* { dg-final { scan-assembler {\mvrlh\M} } } */
+/* { dg-final { scan-assembler {\mvrlb\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-rotate-4.c b/gcc/testsuite/gcc.target/powerpc/vec-rotate-4.c
new file mode 100644
index 00000000000..75f08f07ba7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-rotate-4.c
@@ -0,0 +1,19 @@
+/* { dg-options "-O3 -mdejagnu-cpu=power8" } */
+
+/* Check vectorizer can exploit vector rotation instructions on Power8, mainly
+   for the case rotation count isn't const number.
+
+   Check for vrld which is available on Power8 and above.  */
+
+#define N 256
+unsigned long long sud[N], rud[N];
+extern unsigned char rot_cnt;
+
+void
+testULL ()
+{
+  for (int i = 0; i < 256; ++i)
+    rud[i] = (sud[i] >> rot_cnt) | (sud[i] << (sizeof (sud[0]) * 8 - rot_cnt));
+}
+
+/* { dg-final { scan-assembler {\mvrld\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c
deleted file mode 100644
index f035a578292..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* { dg-options "-O3" } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-
-/* Check vectorizer can exploit vector rotation instructions on Power, mainly
-   for the case rotation count is const number.
-
-   Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */
-
-#define N 256
-unsigned int suw[N], ruw[N];
-unsigned short suh[N], ruh[N];
-unsigned char sub[N], rub[N];
-
-void
-testUW ()
-{
-  for (int i = 0; i < 256; ++i)
-    ruw[i] = (suw[i] >> 8) | (suw[i] << (sizeof (suw[0]) * 8 - 8));
-}
-
-void
-testUH ()
-{
-  for (int i = 0; i < 256; ++i)
-    ruh[i] = (unsigned short) (suh[i] >> 9)
-	     | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - 9));
-}
-
-void
-testUB ()
-{
-  for (int i = 0; i < 256; ++i)
-    rub[i] = (unsigned char) (sub[i] >> 5)
-	     | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - 5));
-}
-
-/* { dg-final { scan-assembler {\mvrlw\M} } } */
-/* { dg-final { scan-assembler {\mvrlh\M} } } */
-/* { dg-final { scan-assembler {\mvrlb\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c
deleted file mode 100644
index 23598958ef2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* { dg-options "-O3 -mdejagnu-cpu=power8" } */
-
-/* Check vectorizer can exploit vector rotation instructions on Power8, mainly
-   for the case rotation count is const number.
-
-   Check for vrld which is available on Power8 and above.  */
-
-#define N 256
-unsigned long long sud[N], rud[N];
-
-void
-testULL ()
-{
-  for (int i = 0; i < 256; ++i)
-    rud[i] = (sud[i] >> 8) | (sud[i] << (sizeof (sud[0]) * 8 - 8));
-}
-
-/* { dg-final { scan-assembler {\mvrld\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c
deleted file mode 100644
index 5e90ae6fd63..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-options "-O3" } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-
-/* Check vectorizer can exploit vector rotation instructions on Power, mainly
-   for the case rotation count isn't const number.
-
-   Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */
-
-#define N 256
-unsigned int suw[N], ruw[N];
-unsigned short suh[N], ruh[N];
-unsigned char sub[N], rub[N];
-extern unsigned char rot_cnt;
-
-void
-testUW ()
-{
-  for (int i = 0; i < 256; ++i)
-    ruw[i] = (suw[i] >> rot_cnt) | (suw[i] << (sizeof (suw[0]) * 8 - rot_cnt));
-}
-
-void
-testUH ()
-{
-  for (int i = 0; i < 256; ++i)
-    ruh[i] = (unsigned short) (suh[i] >> rot_cnt)
-	     | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - rot_cnt));
-}
-
-void
-testUB ()
-{
-  for (int i = 0; i < 256; ++i)
-    rub[i] = (unsigned char) (sub[i] >> rot_cnt)
-	     | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - rot_cnt));
-}
-
-/* { dg-final { scan-assembler {\mvrlw\M} } } */
-/* { dg-final { scan-assembler {\mvrlh\M} } } */
-/* { dg-final { scan-assembler {\mvrlb\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c
deleted file mode 100644
index 75f08f07ba7..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-options "-O3 -mdejagnu-cpu=power8" } */
-
-/* Check vectorizer can exploit vector rotation instructions on Power8, mainly
-   for the case rotation count isn't const number.
-
-   Check for vrld which is available on Power8 and above.  */
-
-#define N 256
-unsigned long long sud[N], rud[N];
-extern unsigned char rot_cnt;
-
-void
-testULL ()
-{
-  for (int i = 0; i < 256; ++i)
-    rud[i] = (sud[i] >> rot_cnt) | (sud[i] << (sizeof (sud[0]) * 8 - rot_cnt));
-}
-
-/* { dg-final { scan-assembler {\mvrld\M} } } */