From: Clifford Wolf Date: Fri, 8 Mar 2013 07:19:24 +0000 (+0100) Subject: Split extract -attr into extract -cell_attr and -wire_attr X-Git-Tag: yosys-0.2.0~733 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef4f1c55b6b80ebf61ae509e2e0ab4e3c1eac2bc;p=yosys.git Split extract -attr into extract -cell_attr and -wire_attr --- diff --git a/passes/extract/extract.cc b/passes/extract/extract.cc index 4909126a7..d25af324e 100644 --- a/passes/extract/extract.cc +++ b/passes/extract/extract.cc @@ -34,11 +34,11 @@ namespace class SubCircuitSolver : public SubCircuit::Solver { public: - std::set attr_compare; + std::set cell_attr, wire_attr; - bool compareAttributes(const std::map &needleAttr, const std::map &haystackAttr) + bool compareAttributes(const std::set &attr, const std::map &needleAttr, const std::map &haystackAttr) { - for (auto &it : attr_compare) { + for (auto &it : attr) { size_t nc = needleAttr.count(it), hc = haystackAttr.count(it); if (nc != hc || (nc > 0 && needleAttr.at(it) != haystackAttr.at(it))) return false; @@ -49,33 +49,33 @@ namespace virtual bool userCompareNodes(const std::string &, const std::string &, void *needleUserData, const std::string &, const std::string &, void *haystackUserData, const std::map &portMapping) { - if (attr_compare.size() == 0) - return true; - RTLIL::Cell *needleCell = (RTLIL::Cell*) needleUserData; RTLIL::Cell *haystackCell = (RTLIL::Cell*) haystackUserData; - if (!compareAttributes(needleCell->attributes, haystackCell->attributes)) + if (cell_attr.size() > 0 && !compareAttributes(cell_attr, needleCell->attributes, haystackCell->attributes)) return false; - RTLIL::Wire *lastNeedleWire = NULL; - RTLIL::Wire *lastHaystackWire = NULL; - std::map emptyAttr; - - for (auto &conn : needleCell->connections) + if (wire_attr.size() > 0) { - RTLIL::SigSpec needleSig = conn.second; - RTLIL::SigSpec haystackSig = haystackCell->connections.at(portMapping.at(conn.first)); - - needleSig.expand(); - haystackSig.expand(); - - for (int i = 0; i < std::min(needleSig.width, haystackSig.width); i++) { - RTLIL::Wire *needleWire = needleSig.chunks.at(i).wire, *haystackWire = haystackSig.chunks.at(i).wire; - if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire) - if (!compareAttributes(needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr)) - return false; - lastNeedleWire = needleWire, lastHaystackWire = haystackWire; + RTLIL::Wire *lastNeedleWire = NULL; + RTLIL::Wire *lastHaystackWire = NULL; + std::map emptyAttr; + + for (auto &conn : needleCell->connections) + { + RTLIL::SigSpec needleSig = conn.second; + RTLIL::SigSpec haystackSig = haystackCell->connections.at(portMapping.at(conn.first)); + + needleSig.expand(); + haystackSig.expand(); + + for (int i = 0; i < std::min(needleSig.width, haystackSig.width); i++) { + RTLIL::Wire *needleWire = needleSig.chunks.at(i).wire, *haystackWire = haystackSig.chunks.at(i).wire; + if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire) + if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr)) + return false; + lastNeedleWire = needleWire, lastHaystackWire = haystackWire; + } } } @@ -340,8 +340,11 @@ struct ExtractPass : public Pass { log(" Register a valid permutation of swapable ports for a needle\n"); log(" cell type. This option can be used multiple times.\n"); log("\n"); - log(" -attr \n"); - log(" Attributes with the given name must match (cells and wires).\n"); + log(" -cell_attr \n"); + log(" Attributes on cells with the given name must match.\n"); + log("\n"); + log(" -wire_attr \n"); + log(" Attributes on wires with the given name must match.\n"); log("\n"); log("This pass does not operate on modules with uprocessed processes in it.\n"); log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n"); @@ -477,8 +480,12 @@ struct ExtractPass : public Pass { solver.addSwappablePortsPermutation(type, map); continue; } - if (args[argidx] == "-attr" && argidx+1 < args.size()) { - solver.attr_compare.insert(RTLIL::escape_id(args[++argidx])); + if (args[argidx] == "-cell_attr" && argidx+1 < args.size()) { + solver.cell_attr.insert(RTLIL::escape_id(args[++argidx])); + continue; + } + if (args[argidx] == "-wire_attr" && argidx+1 < args.size()) { + solver.wire_attr.insert(RTLIL::escape_id(args[++argidx])); continue; } break;