From: Palmer Dabbelt <palmer@dabbelt.com>
Date: Mon, 6 Feb 2017 21:38:43 +0000 (+0000)
Subject: RISC-V Port: Regenerate gcc/configure
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef57f7d6b1a0568f58eff04a1b27de4a22a5e07f;p=gcc.git

RISC-V Port: Regenerate gcc/configure

From-SVN: r245225
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2ea85e5a608..b8e32c15c7a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -31,6 +31,7 @@
 	* doc/install.texi: Add RISC-V entries.
 	* doc/invoke.texi: Add RISC-V options section.
 	* doc/md.texi: Add RISC-V constraints section.
+	* configure: Regenerated.
 
 2017-02-06  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
diff --git a/gcc/configure b/gcc/configure
index c9e43fb80e3..5359a4e6ee5 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -24156,6 +24156,17 @@ x3:	.space 4
 	tls_first_minor=14
 	tls_as_opt="-a32 --fatal-warnings"
 	;;
+  riscv*-*-*)
+    conftest_s='
+	.section .tdata,"awT",@progbits
+x:	.word 2
+	.text
+	la.tls.gd a0,x
+        call __tls_get_addr'
+	tls_first_major=2
+	tls_first_minor=21
+	tls_as_opt='--fatal-warnings'
+	;;
   s390-*-*)
     conftest_s='
 	.section ".tdata","awT",@progbits
@@ -27516,8 +27527,8 @@ esac
 # version to the per-target configury.
 case "$cpu_type" in
   aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \
-  | mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
-  | visium | xstormy16 | xtensa)
+  | mips | nios2 | pa | riscv | rs6000 | score | sparc | spu | tilegx \
+  | tilepro | visium | xstormy16 | xtensa)
     insn="nop"
     ;;
   ia64 | s390)